clk_divider.flow.rpt

clock_spliter 採用彈性設計 , 可調整週期寬度.

Flow report for clk_divider
Fri Feb 15 15:05:07 2008
Quartus II Version 7.1 Build 156 04/30/2007 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Non-Default Global Settings
  5. Flow Elapsed Time
  6. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------+
; Flow Summary                                                      ;
+-------------------------+-----------------------------------------+
; Flow Status             ; Successful - Fri Feb 15 15:05:06 2008   ;
; Quartus II Version      ; 7.1 Build 156 04/30/2007 SJ Web Edition ;
; Revision Name           ; clk_divider                             ;
; Top-level Entity Name   ; clk_divider                             ;
; Family                  ; MAX3000A                                ;
; Device                  ; EPM3256ATC144-10                        ;
; Timing Models           ; Final                                   ;
; Met timing requirements ; Yes                                     ;
; Total macrocells        ; 5 / 256 ( 2 % )                         ;
; Total pins              ; 7 / 116 ( 6 % )                         ;
+-------------------------+-----------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 02/15/2008 15:04:14 ;
; Main task         ; Compilation         ;
; Revision Name     ; clk_divider         ;
+-------------------+---------------------+


+--------------------------------------------------------------------+
; Flow Non-Default Global Settings                                   ;
+-----------------+-------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-----------------+-------+---------------+-------------+------------+


+----------------------------------------+
; Flow Elapsed Time                      ;
+-------------------------+--------------+
; Module Name             ; Elapsed Time ;
+-------------------------+--------------+
; Analysis & Synthesis    ; 00:00:09     ;
; Fitter                  ; 00:00:04     ;
; Assembler               ; 00:00:10     ;
; Classic Timing Analyzer ; 00:00:06     ;
; Total                   ; 00:00:29     ;
+-------------------------+--------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off clk_divider -c clk_divider
quartus_fit --read_settings_files=off --write_settings_files=off clk_divider -c clk_divider
quartus_asm --read_settings_files=off --write_settings_files=off clk_divider -c clk_divider
quartus_tan --read_settings_files=off --write_settings_files=off clk_divider -c clk_divider