ddf1.vhd

来自「d,jk,rs触发器的vhdl语言实现」· VHDL 代码 · 共 21 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DDF1 IS
PORT
(
D,CLK:	IN STD_LOGIC;
Q:	OUT STD_LOGIC
);
END DDF1;

ARCHITECTURE A1 OF DDF1 IS
BEGIN
PROCESS(CLK)
BEGIN
IF CLK' EVENT AND CLK='1' THEN
Q<=D;
END IF;

END PROCESS;
END A1;