rscfq.vhd

来自「d,jk,rs触发器的vhdl语言实现」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all;
 entity rscfq is
	port(p,s,r:in std_logic;
		 q:out std_logic
);
end rscfq;

architecture rs of rscfq is
begin 	
	process(p,s,r)
		begin
			if(s='0' and r='1')then
				q<='1';
			elsif(s='1' and r='0')then
				q<='0';
			elsif(s='1' and r='1')then
				q<=p;
			else
				q<='X';
			end if;
			end process;
end rs;