rscfq.rpt

d,jk,rs触发器的vhdl语言实现

  98      -    B    --      INPUT               0    0    0    1  s


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
$ = Driven by fast output logic cell


Device-Specific Information:                  c:\max2work\zhou\rscfq\rscfq.rpt
rscfq

** OUTPUTS **

       Fed By                                  Fan-In    Fan-Out
 Pin     LC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
  10      -    B    --     OUTPUT               0    1    0    0  q


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
$ = Driven by fast output logic cell


Device-Specific Information:                  c:\max2work\zhou\rscfq\rscfq.rpt
rscfq

** BURIED LOGIC **

                                               Fan-In    Fan-Out
 IOC     LC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
   -      2    B    12        OR2              3    0    1    0  :66


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
$ = Driven by fast output logic cell
p = Packed register


Device-Specific Information:                  c:\max2work\zhou\rscfq\rscfq.rpt
rscfq

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/20(  0%)      0/20(  0%)     0/20(  0%)
B:       1/ 96(  1%)     1/ 48(  2%)     2/ 48(  4%)    2/20( 10%)      1/20(  5%)     0/20(  0%)
C:       1/ 96(  1%)     0/ 48(  0%)     0/ 48(  0%)    1/20(  5%)      0/20(  0%)     0/20(  0%)
D:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/20(  0%)      0/20(  0%)     0/20(  0%)
E:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/20(  0%)      0/20(  0%)     0/20(  0%)
F:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/20(  0%)      0/20(  0%)     0/20(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/20(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/20(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      1/20(  5%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/20(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/20(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/20(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/20(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/20(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/20(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/20(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/20(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/20(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/20(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/20(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/20(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      0/20(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/20(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/20(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/20(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/20(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/20(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/20(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                  c:\max2work\zhou\rscfq\rscfq.rpt
rscfq

** EQUATIONS **

p        : INPUT;
r        : INPUT;
s        : INPUT;

-- Node name is 'q' 
-- Equation name is 'q', type is output 
q        =  _LC2_B12;

-- Node name is ':66' 
-- Equation name is '_LC2_B12', type is buried 
_LC2_B12 = LCELL( _EQ001);
  _EQ001 =  r & !s
         #  p &  r;



Project Information                           c:\max2work\zhou\rscfq\rscfq.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX6000' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 16,902K