📄 jk.rpt
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** BURIED LOGIC **
Fan-In Fan-Out
IOC LC Row Col Primitive Code INP FBK OUT FBK Name
- 2 C 02 AND2 s 2 0 0 2 Q1~1 (~8~1)
- 6 C 02 OR2 s 2 1 0 3 Q1~2 (~8~2)
- 3 B 01 OR2 s 2 2 1 1 Q1~3 (~8~3)
- 4 B 01 DFF 3 3 0 1 Q1 (:8)
- 1 C 02 OR2 s 2 1 0 3 Q2~1 (~9~1)
- 2 B 01 OR2 s 2 2 1 1 Q2~2 (~9~2)
- 5 B 01 DFF 3 3 0 1 Q2 (:9)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
$ = Driven by fast output logic cell
p = Packed register
Device-Specific Information: c:\max2work\zhou\jk\jk.rpt
jk
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
B: 2/ 96( 2%) 6/ 48( 12%) 0/ 48( 0%) 2/20( 10%) 2/20( 10%) 0/20( 0%)
C: 2/ 96( 2%) 0/ 48( 0%) 0/ 48( 0%) 2/20( 10%) 0/20( 0%) 0/20( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
E: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
F: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/20( 0%) 0/20( 0%) 0/20( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/20( 10%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 3/20( 15%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/20( 5%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/20( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\max2work\zhou\jk\jk.rpt
jk
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 2 clk
Device-Specific Information: c:\max2work\zhou\jk\jk.rpt
jk
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 2 Q1~1
Device-Specific Information: c:\max2work\zhou\jk\jk.rpt
jk
** EQUATIONS **
clk : INPUT;
clr : INPUT;
j : INPUT;
k : INPUT;
reset : INPUT;
-- Node name is 'Q'
-- Equation name is 'Q', type is output
Q = _LC3_B1;
-- Node name is 'QN'
-- Equation name is 'QN', type is output
QN = _LC2_B1;
-- Node name is '~8~1' = 'Q1~1'
-- Equation name is '~8~1', location is LC2_C2, type is buried.
-- synthesized logic cell
_LC2_C2 = LCELL( _EQ001);
_EQ001 = clr & reset;
-- Node name is '~8~2' = 'Q1~2'
-- Equation name is '~8~2', location is LC6_C2, type is buried.
-- synthesized logic cell
_LC6_C2 = LCELL( _EQ002);
_EQ002 = !clr
# _LC6_C2 & reset;
-- Node name is '~8~3' = 'Q1~3'
-- Equation name is '~8~3', location is LC3_B1, type is buried.
-- synthesized logic cell
_LC3_B1 = LCELL( _EQ003);
_EQ003 = clr & !reset
# clr & _LC6_C2 & Q1
# clr & !_LC6_C2 & !Q1;
-- Node name is ':8' = 'Q1'
-- Equation name is 'Q1', location is LC4_B1, type is buried.
Q1 = DFF( _EQ004, clk, _LC2_C2, VCC);
_EQ004 = !k & _LC3_B1 & _LC6_C2
# j & !_LC3_B1 & _LC6_C2
# j & !k & _LC6_C2
# !j & !_LC3_B1 & !_LC6_C2
# k & _LC3_B1 & !_LC6_C2
# !j & k & !_LC6_C2;
-- Node name is '~9~1' = 'Q2~1'
-- Equation name is '~9~1', location is LC1_C2, type is buried.
-- synthesized logic cell
_LC1_C2 = LCELL( _EQ005);
_EQ005 = !reset
# clr & _LC1_C2;
-- Node name is '~9~2' = 'Q2~2'
-- Equation name is '~9~2', location is LC2_B1, type is buried.
-- synthesized logic cell
_LC2_B1 = LCELL( _EQ006);
_EQ006 = !clr & reset
# _LC1_C2 & Q2 & reset
# !_LC1_C2 & !Q2 & reset;
-- Node name is ':9' = 'Q2'
-- Equation name is 'Q2', location is LC5_B1, type is buried.
Q2 = DFF( _EQ007, clk, _LC2_C2, VCC);
_EQ007 = !j & _LC1_C2 & _LC2_B1
# !j & k & _LC1_C2
# k & _LC1_C2 & !_LC2_B1
# j & !k & !_LC1_C2
# j & !_LC1_C2 & _LC2_B1
# !k & !_LC1_C2 & !_LC2_B1;
Project Information c:\max2work\zhou\jk\jk.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX6000' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,129K
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