jk.vhd

d,jk,rs触发器的vhdl语言实现

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity jk is
port(
     j,k:in std_logic;
     reset,clr: in std_logic; 
     clk: in std_logic;
     Q,QN:out std_logic);
end jk;
architecture behave of jk is
signal Q1,Q2:std_logic;
begin
process(reset,clr,clk,j,k)
begin
 if(reset='0')then
    Q1<='1';
    Q2<='0';
 elsif(clr='0')then
    Q1<='0';
    Q2<='1';
 elsif(clk'event and clk='1')then
      if(j='0' and k='0')then
         Q1<=Q1;Q2<=Q2;
      elsif(j='0' and k='1')then
         Q1<='0';Q2<='1';
      elsif(j='1' and k='0')then
         Q1<='1';Q2<='0';
      elsif(j='1' and k='1')then
         Q1<=not Q1;Q2<=not Q2;
      end if;
 end if;
Q<=Q1;QN<=Q2;
end process;

end behave;