adder8.fit.qmsg

很多vhdl例程代码

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.737 ns register register " "Info: Estimated most critical path is register to register delay of 5.737 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns key_led:inst1\|count\[8\] 1 REG LAB_X23_Y14 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X23_Y14; Fanout = 4; REG Node = 'key_led:inst1\|count\[8\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "" { key_led:inst1|count[8] } "NODE_NAME" } "" } } { "key_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/key_led.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.155 ns) + CELL(0.292 ns) 1.447 ns key_led:inst1\|LessThan~281 2 COMB LAB_X23_Y15 1 " "Info: 2: + IC(1.155 ns) + CELL(0.292 ns) = 1.447 ns; Loc. = LAB_X23_Y15; Fanout = 1; COMB Node = 'key_led:inst1\|LessThan~281'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "1.447 ns" { key_led:inst1|count[8] key_led:inst1|LessThan~281 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.074 ns) + CELL(0.590 ns) 2.111 ns key_led:inst1\|LessThan~282 3 COMB LAB_X23_Y15 2 " "Info: 3: + IC(0.074 ns) + CELL(0.590 ns) = 2.111 ns; Loc. = LAB_X23_Y15; Fanout = 2; COMB Node = 'key_led:inst1\|LessThan~282'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "0.664 ns" { key_led:inst1|LessThan~281 key_led:inst1|LessThan~282 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.781 ns) + CELL(0.590 ns) 3.482 ns key_led:inst1\|LessThan~284 4 COMB LAB_X23_Y14 17 " "Info: 4: + IC(0.781 ns) + CELL(0.590 ns) = 3.482 ns; Loc. = LAB_X23_Y14; Fanout = 17; COMB Node = 'key_led:inst1\|LessThan~284'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "1.371 ns" { key_led:inst1|LessThan~282 key_led:inst1|LessThan~284 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.143 ns) + CELL(1.112 ns) 5.737 ns key_led:inst1\|count\[6\] 5 REG LAB_X23_Y15 4 " "Info: 5: + IC(1.143 ns) + CELL(1.112 ns) = 5.737 ns; Loc. = LAB_X23_Y15; Fanout = 4; REG Node = 'key_led:inst1\|count\[6\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "2.255 ns" { key_led:inst1|LessThan~284 key_led:inst1|count[6] } "NODE_NAME" } "" } } { "key_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/key_led.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.584 ns 45.04 % " "Info: Total cell delay = 2.584 ns ( 45.04 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.153 ns 54.96 % " "Info: Total interconnect delay = 3.153 ns ( 54.96 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "5.737 ns" { key_led:inst1|count[8] key_led:inst1|LessThan~281 key_led:inst1|LessThan~282 key_led:inst1|LessThan~284 key_led:inst1|count[6] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 2 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 2%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "5 " "Warning: The following 5 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "led\[7\] VCC " "Info: Pin led\[7\] has VCC driving its datain port" {  } { { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/Block1.bdf" { { 64 520 696 80 "led\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "led\[7\]" } } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "" { led[7] } "NODE_NAME" } "" } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/adder8.fld" "" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/adder8.fld" "" "" { led[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "led\[6\] VCC " "Info: Pin led\[6\] has VCC driving its datain port" {  } { { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/Block1.bdf" { { 64 520 696 80 "led\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "led\[6\]" } } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "" { led[6] } "NODE_NAME" } "" } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/adder8.fld" "" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/adder8.fld" "" "" { led[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "led\[5\] VCC " "Info: Pin led\[5\] has VCC driving its datain port" {  } { { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/Block1.bdf" { { 64 520 696 80 "led\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "led\[5\]" } } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "" { led[5] } "NODE_NAME" } "" } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/adder8.fld" "" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/adder8.fld" "" "" { led[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "led\[4\] VCC " "Info: Pin led\[4\] has VCC driving its datain port" {  } { { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/Block1.bdf" { { 64 520 696 80 "led\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "led\[4\]" } } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "" { led[4] } "NODE_NAME" } "" } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/adder8.fld" "" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/adder8.fld" "" "" { led[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seg\[7\] VCC " "Info: Pin seg\[7\] has VCC driving its datain port" {  } { { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/Block1.bdf" { { 80 512 688 96 "seg\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "seg\[7\]" } } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "" { seg[7] } "NODE_NAME" } "" } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/adder8.fld" "" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/adder8.fld" "" "" { seg[7] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 18 10:51:15 2006 " "Info: Processing ended: Mon Sep 18 10:51:15 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0}  } {  } 0}