adder8.tan.qmsg

很多vhdl例程代码

{ "Info" "ITDB_FULL_TCO_RESULT" "clock_48M led\[3\] key_led:inst1\|bin_r\[3\] 9.710 ns register " "Info: tco from clock \"clock_48M\" to destination pin \"led\[3\]\" through register \"key_led:inst1\|bin_r\[3\]\" is 9.710 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_48M source 2.942 ns + Longest register " "Info: + Longest clock path from clock \"clock_48M\" to source register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock_48M 1 CLK PIN_28 85 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 85; CLK Node = 'clock_48M'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "" { clock_48M } "NODE_NAME" } "" } } { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/Block1.bdf" { { 64 96 264 80 "clock_48M" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns key_led:inst1\|bin_r\[3\] 2 REG LC_X27_Y10_N3 2 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X27_Y10_N3; Fanout = 2; REG Node = 'key_led:inst1\|bin_r\[3\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "1.473 ns" { clock_48M key_led:inst1|bin_r[3] } "NODE_NAME" } "" } } { "key_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/key_led.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.10 % " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns 25.90 % " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "2.942 ns" { clock_48M key_led:inst1|bin_r[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.942 ns" { clock_48M clock_48M~out0 key_led:inst1|bin_r[3] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "key_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/key_led.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.544 ns + Longest register pin " "Info: + Longest register to pin delay is 6.544 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns key_led:inst1\|bin_r\[3\] 1 REG LC_X27_Y10_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X27_Y10_N3; Fanout = 2; REG Node = 'key_led:inst1\|bin_r\[3\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "" { key_led:inst1|bin_r[3] } "NODE_NAME" } "" } } { "key_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/key_led.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.420 ns) + CELL(2.124 ns) 6.544 ns led\[3\] 2 PIN PIN_55 0 " "Info: 2: + IC(4.420 ns) + CELL(2.124 ns) = 6.544 ns; Loc. = PIN_55; Fanout = 0; PIN Node = 'led\[3\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "6.544 ns" { key_led:inst1|bin_r[3] led[3] } "NODE_NAME" } "" } } { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/Block1.bdf" { { 64 520 696 80 "led\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 32.46 % " "Info: Total cell delay = 2.124 ns ( 32.46 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.420 ns 67.54 % " "Info: Total interconnect delay = 4.420 ns ( 67.54 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "6.544 ns" { key_led:inst1|bin_r[3] led[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.544 ns" { key_led:inst1|bin_r[3] led[3] } { 0.000ns 4.420ns } { 0.000ns 2.124ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "2.942 ns" { clock_48M key_led:inst1|bin_r[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.942 ns" { clock_48M clock_48M~out0 key_led:inst1|bin_r[3] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "6.544 ns" { key_led:inst1|bin_r[3] led[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.544 ns" { key_led:inst1|bin_r[3] led[3] } { 0.000ns 4.420ns } { 0.000ns 2.124ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "key_led:inst1\|dout1\[4\] key\[4\] clock_48M -4.270 ns register " "Info: th for register \"key_led:inst1\|dout1\[4\]\" (data pin = \"key\[4\]\", clock pin = \"clock_48M\") is -4.270 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_48M destination 2.910 ns + Longest register " "Info: + Longest clock path from clock \"clock_48M\" to destination register is 2.910 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock_48M 1 CLK PIN_28 85 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 85; CLK Node = 'clock_48M'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "" { clock_48M } "NODE_NAME" } "" } } { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/Block1.bdf" { { 64 96 264 80 "clock_48M" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.730 ns) + CELL(0.711 ns) 2.910 ns key_led:inst1\|dout1\[4\] 2 REG LC_X26_Y9_N6 3 " "Info: 2: + IC(0.730 ns) + CELL(0.711 ns) = 2.910 ns; Loc. = LC_X26_Y9_N6; Fanout = 3; REG Node = 'key_led:inst1\|dout1\[4\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "1.441 ns" { clock_48M key_led:inst1|dout1[4] } "NODE_NAME" } "" } } { "key_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/key_led.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.91 % " "Info: Total cell delay = 2.180 ns ( 74.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.730 ns 25.09 % " "Info: Total interconnect delay = 0.730 ns ( 25.09 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "2.910 ns" { clock_48M key_led:inst1|dout1[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.910 ns" { clock_48M clock_48M~out0 key_led:inst1|dout1[4] } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "key_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/key_led.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.195 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.195 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns key\[4\] 1 PIN PIN_143 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_143; Fanout = 1; PIN Node = 'key\[4\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "" { key[4] } "NODE_NAME" } "" } } { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/Block1.bdf" { { 80 56 224 96 "key\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.611 ns) + CELL(0.115 ns) 7.195 ns key_led:inst1\|dout1\[4\] 2 REG LC_X26_Y9_N6 3 " "Info: 2: + IC(5.611 ns) + CELL(0.115 ns) = 7.195 ns; Loc. = LC_X26_Y9_N6; Fanout = 3; REG Node = 'key_led:inst1\|dout1\[4\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "5.726 ns" { key[4] key_led:inst1|dout1[4] } "NODE_NAME" } "" } } { "key_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/key_led.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns 22.02 % " "Info: Total cell delay = 1.584 ns ( 22.02 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.611 ns 77.98 % " "Info: Total interconnect delay = 5.611 ns ( 77.98 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "7.195 ns" { key[4] key_led:inst1|dout1[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.195 ns" { key[4] key[4]~out0 key_led:inst1|dout1[4] } { 0.000ns 0.000ns 5.611ns } { 0.000ns 1.469ns 0.115ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "2.910 ns" { clock_48M key_led:inst1|dout1[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.910 ns" { clock_48M clock_48M~out0 key_led:inst1|dout1[4] } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "7.195 ns" { key[4] key_led:inst1|dout1[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.195 ns" { key[4] key[4]~out0 key_led:inst1|dout1[4] } { 0.000ns 0.000ns 5.611ns } { 0.000ns 1.469ns 0.115ns } } }  } 0}
{ "Info" "ITAN_REQUIREMENTS_MET" "" "Info: All timing requirements were met. See Report window for more details." {  } {  } 0}