📄 adder8.tan.qmsg
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{ "Info" "ITDB_FULL_SLACK_RESULT" "clock_48M register key_led:inst1\|count\[9\] register key_led:inst1\|count\[6\] 13.177 ns " "Info: Slack time is 13.177 ns for clock \"clock_48M\" between source register \"key_led:inst1\|count\[9\]\" and destination register \"key_led:inst1\|count\[6\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "146.56 MHz 6.823 ns " "Info: Fmax is 146.56 MHz (period= 6.823 ns)" { } { } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "19.739 ns + Largest register register " "Info: + Largest register to register requirement is 19.739 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.000 ns + " "Info: + Setup relationship between source and destination is 20.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 20.000 ns " "Info: + Latch edge is 20.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clock_48M 20.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"clock_48M\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0} } { } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clock_48M 20.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"clock_48M\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0} } { } 0} } { } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_48M destination 2.962 ns + Shortest register " "Info: + Shortest clock path from clock \"clock_48M\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock_48M 1 CLK PIN_28 85 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 85; CLK Node = 'clock_48M'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "" { clock_48M } "NODE_NAME" } "" } } { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/Block1.bdf" { { 64 96 264 80 "clock_48M" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns key_led:inst1\|count\[6\] 2 REG LC_X23_Y15_N8 4 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X23_Y15_N8; Fanout = 4; REG Node = 'key_led:inst1\|count\[6\]'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "1.493 ns" { clock_48M key_led:inst1|count[6] } "NODE_NAME" } "" } } { "key_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/key_led.vhd" 26 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.60 % " "Info: Total cell delay = 2.180 ns ( 73.60 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns 26.40 % " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" { } { } 0} } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "2.962 ns" { clock_48M key_led:inst1|count[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.962 ns" { clock_48M clock_48M~out0 key_led:inst1|count[6] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_48M source 2.962 ns - Longest register " "Info: - Longest clock path from clock \"clock_48M\" to source register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock_48M 1 CLK PIN_28 85 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 85; CLK Node = 'clock_48M'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "" { clock_48M } "NODE_NAME" } "" } } { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/Block1.bdf" { { 64 96 264 80 "clock_48M" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns key_led:inst1\|count\[9\] 2 REG LC_X23_Y14_N1 4 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X23_Y14_N1; Fanout = 4; REG Node = 'key_led:inst1\|count\[9\]'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "1.493 ns" { clock_48M key_led:inst1|count[9] } "NODE_NAME" } "" } } { "key_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/key_led.vhd" 26 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.60 % " "Info: Total cell delay = 2.180 ns ( 73.60 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns 26.40 % " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" { } { } 0} } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "2.962 ns" { clock_48M key_led:inst1|count[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.962 ns" { clock_48M clock_48M~out0 key_led:inst1|count[9] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "2.962 ns" { clock_48M key_led:inst1|count[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.962 ns" { clock_48M clock_48M~out0 key_led:inst1|count[6] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "2.962 ns" { clock_48M key_led:inst1|count[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.962 ns" { clock_48M clock_48M~out0 key_led:inst1|count[9] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" { } { { "key_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/key_led.vhd" 26 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" { } { { "key_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/key_led.vhd" 26 -1 0 } } } 0} } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "2.962 ns" { clock_48M key_led:inst1|count[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.962 ns" { clock_48M clock_48M~out0 key_led:inst1|count[6] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "2.962 ns" { clock_48M key_led:inst1|count[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.962 ns" { clock_48M clock_48M~out0 key_led:inst1|count[9] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.562 ns - Longest register register " "Info: - Longest register to register delay is 6.562 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns key_led:inst1\|count\[9\] 1 REG LC_X23_Y14_N1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y14_N1; Fanout = 4; REG Node = 'key_led:inst1\|count\[9\]'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "" { key_led:inst1|count[9] } "NODE_NAME" } "" } } { "key_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/key_led.vhd" 26 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.242 ns) + CELL(0.442 ns) 1.684 ns key_led:inst1\|LessThan~281 2 COMB LC_X23_Y15_N0 1 " "Info: 2: + IC(1.242 ns) + CELL(0.442 ns) = 1.684 ns; Loc. = LC_X23_Y15_N0; Fanout = 1; COMB Node = 'key_led:inst1\|LessThan~281'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "1.684 ns" { key_led:inst1|count[9] key_led:inst1|LessThan~281 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.411 ns) + CELL(0.442 ns) 2.537 ns key_led:inst1\|LessThan~282 3 COMB LC_X23_Y15_N1 2 " "Info: 3: + IC(0.411 ns) + CELL(0.442 ns) = 2.537 ns; Loc. = LC_X23_Y15_N1; Fanout = 2; COMB Node = 'key_led:inst1\|LessThan~282'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "0.853 ns" { key_led:inst1|LessThan~281 key_led:inst1|LessThan~282 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.213 ns) + CELL(0.442 ns) 4.192 ns key_led:inst1\|LessThan~284 4 COMB LC_X23_Y14_N9 17 " "Info: 4: + IC(1.213 ns) + CELL(0.442 ns) = 4.192 ns; Loc. = LC_X23_Y14_N9; Fanout = 17; COMB Node = 'key_led:inst1\|LessThan~284'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "1.655 ns" { key_led:inst1|LessThan~282 key_led:inst1|LessThan~284 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.258 ns) + CELL(1.112 ns) 6.562 ns key_led:inst1\|count\[6\] 5 REG LC_X23_Y15_N8 4 " "Info: 5: + IC(1.258 ns) + CELL(1.112 ns) = 6.562 ns; Loc. = LC_X23_Y15_N8; Fanout = 4; REG Node = 'key_led:inst1\|count\[6\]'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "2.370 ns" { key_led:inst1|LessThan~284 key_led:inst1|count[6] } "NODE_NAME" } "" } } { "key_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/key_led.vhd" 26 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.438 ns 37.15 % " "Info: Total cell delay = 2.438 ns ( 37.15 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.124 ns 62.85 % " "Info: Total interconnect delay = 4.124 ns ( 62.85 % )" { } { } 0} } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "6.562 ns" { key_led:inst1|count[9] key_led:inst1|LessThan~281 key_led:inst1|LessThan~282 key_led:inst1|LessThan~284 key_led:inst1|count[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.562 ns" { key_led:inst1|count[9] key_led:inst1|LessThan~281 key_led:inst1|LessThan~282 key_led:inst1|LessThan~284 key_led:inst1|count[6] } { 0.000ns 1.242ns 0.411ns 1.213ns 1.258ns } { 0.000ns 0.442ns 0.442ns 0.442ns 1.112ns } } } } 0} } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "2.962 ns" { clock_48M key_led:inst1|count[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.962 ns" { clock_48M clock_48M~out0 key_led:inst1|count[6] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "2.962 ns" { clock_48M key_led:inst1|count[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.962 ns" { clock_48M clock_48M~out0 key_led:inst1|count[9] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "6.562 ns" { key_led:inst1|count[9] key_led:inst1|LessThan~281 key_led:inst1|LessThan~282 key_led:inst1|LessThan~284 key_led:inst1|count[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.562 ns" { key_led:inst1|count[9] key_led:inst1|LessThan~281 key_led:inst1|LessThan~282 key_led:inst1|LessThan~284 key_led:inst1|count[6] } { 0.000ns 1.242ns 0.411ns 1.213ns 1.258ns } { 0.000ns 0.442ns 0.442ns 0.442ns 1.112ns } } } } 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clock_48M register key_led:inst1\|dout1\[0\] register key_led:inst1\|dout2\[0\] 873 ps " "Info: Minimum slack time is 873 ps for clock \"clock_48M\" between source register \"key_led:inst1\|dout1\[0\]\" and destination register \"key_led:inst1\|dout2\[0\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.664 ns + Shortest register register " "Info: + Shortest register to register delay is 0.664 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns key_led:inst1\|dout1\[0\] 1 REG LC_X26_Y9_N9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y9_N9; Fanout = 3; REG Node = 'key_led:inst1\|dout1\[0\]'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "" { key_led:inst1|dout1[0] } "NODE_NAME" } "" } } { "key_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/key_led.vhd" 27 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.549 ns) + CELL(0.115 ns) 0.664 ns key_led:inst1\|dout2\[0\] 2 REG LC_X26_Y9_N5 3 " "Info: 2: + IC(0.549 ns) + CELL(0.115 ns) = 0.664 ns; Loc. = LC_X26_Y9_N5; Fanout = 3; REG Node = 'key_led:inst1\|dout2\[0\]'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "0.664 ns" { key_led:inst1|dout1[0] key_led:inst1|dout2[0] } "NODE_NAME" } "" } } { "key_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/key_led.vhd" 27 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns 17.32 % " "Info: Total cell delay = 0.115 ns ( 17.32 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.549 ns 82.68 % " "Info: Total interconnect delay = 0.549 ns ( 82.68 % )" { } { } 0} } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "0.664 ns" { key_led:inst1|dout1[0] key_led:inst1|dout2[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.664 ns" { key_led:inst1|dout1[0] key_led:inst1|dout2[0] } { 0.0ns 0.549ns } { 0.0ns 0.115ns } } } } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clock_48M 20.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"clock_48M\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0} } { } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clock_48M 20.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"clock_48M\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0} } { } 0} } { } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_48M destination 2.910 ns + Longest register " "Info: + Longest clock path from clock \"clock_48M\" to destination register is 2.910 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock_48M 1 CLK PIN_28 85 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 85; CLK Node = 'clock_48M'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "" { clock_48M } "NODE_NAME" } "" } } { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/Block1.bdf" { { 64 96 264 80 "clock_48M" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.730 ns) + CELL(0.711 ns) 2.910 ns key_led:inst1\|dout2\[0\] 2 REG LC_X26_Y9_N5 3 " "Info: 2: + IC(0.730 ns) + CELL(0.711 ns) = 2.910 ns; Loc. = LC_X26_Y9_N5; Fanout = 3; REG Node = 'key_led:inst1\|dout2\[0\]'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "1.441 ns" { clock_48M key_led:inst1|dout2[0] } "NODE_NAME" } "" } } { "key_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/key_led.vhd" 27 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.91 % " "Info: Total cell delay = 2.180 ns ( 74.91 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.730 ns 25.09 % " "Info: Total interconnect delay = 0.730 ns ( 25.09 % )" { } { } 0} } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "2.910 ns" { clock_48M key_led:inst1|dout2[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.910 ns" { clock_48M clock_48M~out0 key_led:inst1|dout2[0] } { 0.0ns 0.0ns 0.73ns } { 0.0ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_48M source 2.910 ns - Shortest register " "Info: - Shortest clock path from clock \"clock_48M\" to source register is 2.910 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock_48M 1 CLK PIN_28 85 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 85; CLK Node = 'clock_48M'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "" { clock_48M } "NODE_NAME" } "" } } { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/Block1.bdf" { { 64 96 264 80 "clock_48M" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.730 ns) + CELL(0.711 ns) 2.910 ns key_led:inst1\|dout1\[0\] 2 REG LC_X26_Y9_N9 3 " "Info: 2: + IC(0.730 ns) + CELL(0.711 ns) = 2.910 ns; Loc. = LC_X26_Y9_N9; Fanout = 3; REG Node = 'key_led:inst1\|dout1\[0\]'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "1.441 ns" { clock_48M key_led:inst1|dout1[0] } "NODE_NAME" } "" } } { "key_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/key_led.vhd" 27 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.91 % " "Info: Total cell delay = 2.180 ns ( 74.91 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.730 ns 25.09 % " "Info: Total interconnect delay = 0.730 ns ( 25.09 % )" { } { } 0} } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "2.910 ns" { clock_48M key_led:inst1|dout1[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.910 ns" { clock_48M clock_48M~out0 key_led:inst1|dout1[0] } { 0.0ns 0.0ns 0.73ns } { 0.0ns 1.469ns 0.711ns } } } } 0} } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "2.910 ns" { clock_48M key_led:inst1|dout2[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.910 ns" { clock_48M clock_48M~out0 key_led:inst1|dout2[0] } { 0.0ns 0.0ns 0.73ns } { 0.0ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "2.910 ns" { clock_48M key_led:inst1|dout1[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.910 ns" { clock_48M clock_48M~out0 key_led:inst1|dout1[0] } { 0.0ns 0.0ns 0.73ns } { 0.0ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" { } { { "key_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/key_led.vhd" 27 -1 0 } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" { } { { "key_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/key_led.vhd" 27 -1 0 } } } 0} } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "2.910 ns" { clock_48M key_led:inst1|dout2[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.910 ns" { clock_48M clock_48M~out0 key_led:inst1|dout2[0] } { 0.0ns 0.0ns 0.73ns } { 0.0ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "2.910 ns" { clock_48M key_led:inst1|dout1[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.910 ns" { clock_48M clock_48M~out0 key_led:inst1|dout1[0] } { 0.0ns 0.0ns 0.73ns } { 0.0ns 1.469ns 0.711ns } } } } 0} } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "0.664 ns" { key_led:inst1|dout1[0] key_led:inst1|dout2[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.664 ns" { key_led:inst1|dout1[0] key_led:inst1|dout2[0] } { 0.0ns 0.549ns } { 0.0ns 0.115ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "2.910 ns" { clock_48M key_led:inst1|dout2[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.910 ns" { clock_48M clock_48M~out0 key_led:inst1|dout2[0] } { 0.0ns 0.0ns 0.73ns } { 0.0ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "2.910 ns" { clock_48M key_led:inst1|dout1[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.910 ns" { clock_48M clock_48M~out0 key_led:inst1|dout1[0] } { 0.0ns 0.0ns 0.73ns } { 0.0ns 1.469ns 0.711ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "key_led:inst1\|dout1\[3\] key\[3\] clock_48M 5.695 ns register " "Info: tsu for register \"key_led:inst1\|dout1\[3\]\" (data pin = \"key\[3\]\", clock pin = \"clock_48M\") is 5.695 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.620 ns + Longest pin register " "Info: + Longest pin to register delay is 8.620 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns key\[3\] 1 PIN PIN_124 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_124; Fanout = 1; PIN Node = 'key\[3\]'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "" { key[3] } "NODE_NAME" } "" } } { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/Block1.bdf" { { 80 56 224 96 "key\[7..0\]" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.842 ns) + CELL(0.309 ns) 8.620 ns key_led:inst1\|dout1\[3\] 2 REG LC_X26_Y15_N9 3 " "Info: 2: + IC(6.842 ns) + CELL(0.309 ns) = 8.620 ns; Loc. = LC_X26_Y15_N9; Fanout = 3; REG Node = 'key_led:inst1\|dout1\[3\]'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "7.151 ns" { key[3] key_led:inst1|dout1[3] } "NODE_NAME" } "" } } { "key_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/key_led.vhd" 27 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns 20.63 % " "Info: Total cell delay = 1.778 ns ( 20.63 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.842 ns 79.37 % " "Info: Total interconnect delay = 6.842 ns ( 79.37 % )" { } { } 0} } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "8.620 ns" { key[3] key_led:inst1|dout1[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.620 ns" { key[3] key[3]~out0 key_led:inst1|dout1[3] } { 0.000ns 0.000ns 6.842ns } { 0.000ns 1.469ns 0.309ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "key_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/key_led.vhd" 27 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_48M destination 2.962 ns - Shortest register " "Info: - Shortest clock path from clock \"clock_48M\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock_48M 1 CLK PIN_28 85 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 85; CLK Node = 'clock_48M'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "" { clock_48M } "NODE_NAME" } "" } } { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/Block1.bdf" { { 64 96 264 80 "clock_48M" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns key_led:inst1\|dout1\[3\] 2 REG LC_X26_Y15_N9 3 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X26_Y15_N9; Fanout = 3; REG Node = 'key_led:inst1\|dout1\[3\]'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "1.493 ns" { clock_48M key_led:inst1|dout1[3] } "NODE_NAME" } "" } } { "key_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/key_led.vhd" 27 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.60 % " "Info: Total cell delay = 2.180 ns ( 73.60 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns 26.40 % " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" { } { } 0} } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "2.962 ns" { clock_48M key_led:inst1|dout1[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.962 ns" { clock_48M clock_48M~out0 key_led:inst1|dout1[3] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "8.620 ns" { key[3] key_led:inst1|dout1[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.620 ns" { key[3] key[3]~out0 key_led:inst1|dout1[3] } { 0.000ns 0.000ns 6.842ns } { 0.000ns 1.469ns 0.309ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8_cmp.qrpt" Compiler "adder8" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/db/adder8.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/" "" "2.962 ns" { clock_48M key_led:inst1|dout1[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.962 ns" { clock_48M clock_48M~out0 key_led:inst1|dout1[3] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } } 0}
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