adder8.map.qmsg

很多vhdl例程代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1.04 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1.04 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 18 10:51:01 2006 " "Info: Processing started: Mon Sep 18 10:51:01 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off adder8 -c adder8 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adder8 -c adder8" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adder8.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file adder8.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 adder8-one " "Info: Found design unit 1: adder8-one" {  } { { "adder8.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/adder8.vhd" 15 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 adder8 " "Info: Found entity 1: adder8" {  } { { "adder8.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/adder8.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Block1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Block1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Block1 " "Info: Found entity 1: Block1" {  } { { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/Block1.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "key_led.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file key_led.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 key_led-one " "Info: Found design unit 1: key_led-one" {  } { { "key_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/key_led.vhd" 20 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 key_led " "Info: Found entity 1: key_led" {  } { { "key_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/key_led.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Block1 " "Info: Elaborating entity \"Block1\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "key_led key_led:inst1 " "Info: Elaborating entity \"key_led\" for hierarchy \"key_led:inst1\"" {  } { { "Block1.bdf" "inst1" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/Block1.bdf" { { 40 304 464 168 "inst1" "" } } } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "key_led.vhd(203) " "Info: VHDL Case Statement information at key_led.vhd(203): OTHERS choice is never selected" {  } { { "key_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/key_led.vhd" 203 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "adder8 adder8:inst " "Info: Elaborating entity \"adder8\" for hierarchy \"adder8:inst\"" {  } { { "Block1.bdf" "inst" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/Block1.bdf" { { 216 304 440 312 "inst" "" } } } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "led\[7\] VCC " "Warning: Pin \"led\[7\]\" stuck at VCC" {  } { { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/Block1.bdf" { { 64 520 696 80 "led\[7..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "led\[6\] VCC " "Warning: Pin \"led\[6\]\" stuck at VCC" {  } { { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/Block1.bdf" { { 64 520 696 80 "led\[7..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "led\[5\] VCC " "Warning: Pin \"led\[5\]\" stuck at VCC" {  } { { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/Block1.bdf" { { 64 520 696 80 "led\[7..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "led\[4\] VCC " "Warning: Pin \"led\[4\]\" stuck at VCC" {  } { { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/Block1.bdf" { { 64 520 696 80 "led\[7..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "seg\[7\] VCC " "Warning: Pin \"seg\[7\]\" stuck at VCC" {  } { { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/Block1.bdf" { { 80 512 688 96 "seg\[7..0\]" "" } } } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "174 " "Info: Implemented 174 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "9 " "Info: Implemented 9 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "24 " "Info: Implemented 24 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "141 " "Info: Implemented 141 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 18 10:51:05 2006 " "Info: Processing ended: Mon Sep 18 10:51:05 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}