adder8.vhd

来自「很多vhdl例程代码」· VHDL 代码 · 共 25 行

LIBRARY	IEEE;
USE		IEEE.STD_LOGIC_1164.ALL;
USE		IEEE.STD_LOGIC_UNSIGNED.ALL;
USE 	IEEE.STD_LOGIC_ARITH.ALL;

ENTITY adder8 IS 
PORT(
	a,b:		IN	STD_LOGIC_VECTOR(7 DOWNTO 0);	
	cin:		IN	STD_LOGIC;
	cout:		OUT	STD_LOGIC;
	sum:		OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ;

ARCHITECTURE one of adder8 IS
SIGNAL 	sum_r:	STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL 	a_r:	STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL	b_r:	STD_LOGIC_VECTOR(8 DOWNTO 0);
BEGIN
	a_r<=a AND "111111111";
	b_r<=b AND "111111111";
	sum_r<=a_r+b_r+cin;	
	cout<=sum_r(8);
	sum<=sum_r(7 DOWNTO 0);
END;