adder8.map.rpt

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+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                           ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                           ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------+
; adder8.vhd                       ; yes             ; User VHDL File                     ; E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/adder8.vhd  ;
; Block1.bdf                       ; yes             ; User Block Diagram/Schematic File  ; E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/Block1.bdf  ;
; key_led.vhd                      ; yes             ; User VHDL File                     ; E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/key_led.vhd ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------+


+-----------------------------------------------+
; Analysis & Synthesis Resource Usage Summary   ;
+-----------------------------------+-----------+
; Resource                          ; Usage     ;
+-----------------------------------+-----------+
; Total logic elements              ; 141       ;
; Total combinational functions     ; 93        ;
;     -- Total 4-input functions    ; 34        ;
;     -- Total 3-input functions    ; 27        ;
;     -- Total 2-input functions    ; 13        ;
;     -- Total 1-input functions    ; 18        ;
;     -- Total 0-input functions    ; 1         ;
; Combinational cells for routing   ; 0         ;
; Total registers                   ; 85        ;
; Total logic cells in carry chains ; 27        ;
; I/O pins                          ; 33        ;
; Maximum fan-out node              ; clock_48M ;
; Maximum fan-out                   ; 85        ;
; Total fan-out                     ; 514       ;
; Average fan-out                   ; 2.95      ;
+-----------------------------------+-----------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                         ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name   ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------+
; |Block1                    ; 141 (0)     ; 85           ; 0           ; 33   ; 0            ; 56 (0)       ; 48 (0)            ; 37 (0)           ; 27 (0)          ; |Block1               ;
;    |adder8:inst|           ; 10 (10)     ; 0            ; 0           ; 0    ; 0            ; 10 (10)      ; 0 (0)             ; 0 (0)            ; 10 (10)         ; |Block1|adder8:inst   ;
;    |key_led:inst1|         ; 131 (131)   ; 85           ; 0           ; 0    ; 0            ; 46 (46)      ; 48 (48)           ; 37 (37)          ; 17 (17)         ; |Block1|key_led:inst1 ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-----------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 85    ;
; Number of registers using Synchronous Clear  ; 17    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 59    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+
; 8:1                ; 3 bits    ; 15 LEs        ; 12 LEs               ; 3 LEs                  ; Yes        ; |Block1|key_led:inst1|disp_dat[1] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_9_adder8/adder8.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1.04 SJ Full Version
    Info: Processing started: Mon Sep 18 10:51:01 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adder8 -c adder8
Info: Found 2 design units, including 1 entities, in source file adder8.vhd
    Info: Found design unit 1: adder8-one
    Info: Found entity 1: adder8
Info: Found 1 design units, including 1 entities, in source file Block1.bdf
    Info: Found entity 1: Block1
Info: Found 2 design units, including 1 entities, in source file key_led.vhd
    Info: Found design unit 1: key_led-one
    Info: Found entity 1: key_led
Info: Elaborating entity "Block1" for the top level hierarchy
Info: Elaborating entity "key_led" for hierarchy "key_led:inst1"
Info: VHDL Case Statement information at key_led.vhd(203): OTHERS choice is never selected
Info: Elaborating entity "adder8" for hierarchy "adder8:inst"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "led[7]" stuck at VCC
    Warning: Pin "led[6]" stuck at VCC
    Warning: Pin "led[5]" stuck at VCC
    Warning: Pin "led[4]" stuck at VCC
    Warning: Pin "seg[7]" stuck at VCC
Info: Implemented 174 device resources after synthesis - the final resource count might be different
    Info: Implemented 9 input pins
    Info: Implemented 24 output pins
    Info: Implemented 141 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
    Info: Processing ended: Mon Sep 18 10:51:05 2006
    Info: Elapsed time: 00:00:05