sled.fit.qmsg

很多vhdl例程代码

{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.143 ns register register " "Info: Estimated most critical path is register to register delay of 5.143 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst1\|Counter\[25\] 1 REG LAB_X9_Y11 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X9_Y11; Fanout = 3; REG Node = 'int_div:inst1\|Counter\[25\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "" { int_div:inst1|Counter[25] } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.405 ns) + CELL(0.114 ns) 1.519 ns int_div:inst1\|reduce_nor~322 2 COMB LAB_X9_Y13 1 " "Info: 2: + IC(1.405 ns) + CELL(0.114 ns) = 1.519 ns; Loc. = LAB_X9_Y13; Fanout = 1; COMB Node = 'int_div:inst1\|reduce_nor~322'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "1.519 ns" { int_div:inst1|Counter[25] int_div:inst1|reduce_nor~322 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.603 ns) + CELL(0.114 ns) 2.236 ns int_div:inst1\|reduce_nor~323 3 COMB LAB_X9_Y13 1 " "Info: 3: + IC(0.603 ns) + CELL(0.114 ns) = 2.236 ns; Loc. = LAB_X9_Y13; Fanout = 1; COMB Node = 'int_div:inst1\|reduce_nor~323'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "0.717 ns" { int_div:inst1|reduce_nor~322 int_div:inst1|reduce_nor~323 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.079 ns) + CELL(0.292 ns) 3.607 ns int_div:inst1\|reduce_nor~0 4 COMB LAB_X10_Y12 11 " "Info: 4: + IC(1.079 ns) + CELL(0.292 ns) = 3.607 ns; Loc. = LAB_X10_Y12; Fanout = 11; COMB Node = 'int_div:inst1\|reduce_nor~0'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "1.371 ns" { int_div:inst1|reduce_nor~323 int_div:inst1|reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.607 ns) 5.143 ns int_div:inst1\|Counter\[23\] 5 REG LAB_X9_Y11 5 " "Info: 5: + IC(0.929 ns) + CELL(0.607 ns) = 5.143 ns; Loc. = LAB_X9_Y11; Fanout = 5; REG Node = 'int_div:inst1\|Counter\[23\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "1.536 ns" { int_div:inst1|reduce_nor~0 int_div:inst1|Counter[23] } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.127 ns 21.91 % " "Info: Total cell delay = 1.127 ns ( 21.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.016 ns 78.09 % " "Info: Total interconnect delay = 4.016 ns ( 78.09 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "5.143 ns" { int_div:inst1|Counter[25] int_div:inst1|reduce_nor~322 int_div:inst1|reduce_nor~323 int_div:inst1|reduce_nor~0 int_div:inst1|Counter[23] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "9 " "Warning: The following 9 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "dig\[7\] GND " "Info: Pin dig\[7\] has GND driving its datain port" {  } { { "sled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.bdf" { { 232 440 616 248 "dig\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dig\[7\]" } } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "" { dig[7] } "NODE_NAME" } "" } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.fld" "" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.fld" "" "" { dig[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "dig\[6\] GND " "Info: Pin dig\[6\] has GND driving its datain port" {  } { { "sled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.bdf" { { 232 440 616 248 "dig\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dig\[6\]" } } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "" { dig[6] } "NODE_NAME" } "" } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.fld" "" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.fld" "" "" { dig[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "dig\[5\] GND " "Info: Pin dig\[5\] has GND driving its datain port" {  } { { "sled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.bdf" { { 232 440 616 248 "dig\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dig\[5\]" } } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "" { dig[5] } "NODE_NAME" } "" } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.fld" "" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.fld" "" "" { dig[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "dig\[4\] GND " "Info: Pin dig\[4\] has GND driving its datain port" {  } { { "sled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.bdf" { { 232 440 616 248 "dig\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dig\[4\]" } } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "" { dig[4] } "NODE_NAME" } "" } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.fld" "" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.fld" "" "" { dig[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "dig\[3\] GND " "Info: Pin dig\[3\] has GND driving its datain port" {  } { { "sled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.bdf" { { 232 440 616 248 "dig\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dig\[3\]" } } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "" { dig[3] } "NODE_NAME" } "" } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.fld" "" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.fld" "" "" { dig[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "dig\[2\] GND " "Info: Pin dig\[2\] has GND driving its datain port" {  } { { "sled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.bdf" { { 232 440 616 248 "dig\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dig\[2\]" } } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "" { dig[2] } "NODE_NAME" } "" } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.fld" "" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.fld" "" "" { dig[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "dig\[1\] GND " "Info: Pin dig\[1\] has GND driving its datain port" {  } { { "sled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.bdf" { { 232 440 616 248 "dig\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dig\[1\]" } } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "" { dig[1] } "NODE_NAME" } "" } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.fld" "" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.fld" "" "" { dig[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "dig\[0\] GND " "Info: Pin dig\[0\] has GND driving its datain port" {  } { { "sled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.bdf" { { 232 440 616 248 "dig\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dig\[0\]" } } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "" { dig[0] } "NODE_NAME" } "" } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.fld" "" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.fld" "" "" { dig[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seg\[7\] VCC " "Info: Pin seg\[7\] has VCC driving its datain port" {  } { { "sled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.bdf" { { 80 600 776 96 "seg\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "seg\[7\]" } } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "" { seg[7] } "NODE_NAME" } "" } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.fld" "" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.fld" "" "" { seg[7] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 15 15:26:41 2006 " "Info: Processing ended: Fri Sep 15 15:26:41 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0}  } {  } 0}