sled.hier_info

很多vhdl例程代码

|sled
dig[0] <= <GND>
dig[1] <= <GND>
dig[2] <= <GND>
dig[3] <= <GND>
dig[4] <= <GND>
dig[5] <= <GND>
dig[6] <= <GND>
dig[7] <= <GND>
seg[0] <= decl7s:inst.seg[0]
seg[1] <= decl7s:inst.seg[1]
seg[2] <= decl7s:inst.seg[2]
seg[3] <= decl7s:inst.seg[3]
seg[4] <= decl7s:inst.seg[4]
seg[5] <= decl7s:inst.seg[5]
seg[6] <= decl7s:inst.seg[6]
seg[7] <= decl7s:inst.seg[7]
clock => int_div:inst1.Clockin


|sled|decl7s:inst
d[0] => Mux~0.IN19
d[0] => Mux~1.IN19
d[0] => Mux~2.IN19
d[0] => Mux~3.IN19
d[0] => Mux~4.IN19
d[0] => Mux~5.IN19
d[0] => Mux~6.IN19
d[1] => Mux~0.IN18
d[1] => Mux~1.IN18
d[1] => Mux~2.IN18
d[1] => Mux~3.IN18
d[1] => Mux~4.IN18
d[1] => Mux~5.IN18
d[1] => Mux~6.IN18
d[2] => Mux~0.IN17
d[2] => Mux~1.IN17
d[2] => Mux~2.IN17
d[2] => Mux~3.IN17
d[2] => Mux~4.IN17
d[2] => Mux~5.IN17
d[2] => Mux~6.IN17
d[3] => Mux~0.IN16
d[3] => Mux~1.IN16
d[3] => Mux~2.IN16
d[3] => Mux~3.IN16
d[3] => Mux~4.IN16
d[3] => Mux~5.IN16
d[3] => Mux~6.IN16
seg[0] <= Mux~6.DB_MAX_OUTPUT_PORT_TYPE
seg[1] <= Mux~5.DB_MAX_OUTPUT_PORT_TYPE
seg[2] <= Mux~4.DB_MAX_OUTPUT_PORT_TYPE
seg[3] <= Mux~3.DB_MAX_OUTPUT_PORT_TYPE
seg[4] <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
seg[5] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
seg[6] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE
seg[7] <= <VCC>


|sled|counter:inst2
clock => lpm_counter:lpm_counter_component.clock
q[0] <= lpm_counter:lpm_counter_component.q[0]
q[1] <= lpm_counter:lpm_counter_component.q[1]
q[2] <= lpm_counter:lpm_counter_component.q[2]
q[3] <= lpm_counter:lpm_counter_component.q[3]


|sled|counter:inst2|lpm_counter:lpm_counter_component
clock => cntr_cs6:auto_generated.clock
clk_en => ~NO_FANOUT~
cnt_en => ~NO_FANOUT~
updown => ~NO_FANOUT~
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
cin => ~NO_FANOUT~
q[0] <= cntr_cs6:auto_generated.q[0]
q[1] <= cntr_cs6:auto_generated.q[1]
q[2] <= cntr_cs6:auto_generated.q[2]
q[3] <= cntr_cs6:auto_generated.q[3]
cout <= <GND>
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|sled|counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
cout <= counter_cella3.COUT
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT


|sled|int_div:inst1
Clockin => Counter[24].CLK
Clockin => Counter[23].CLK
Clockin => Counter[22].CLK
Clockin => Counter[21].CLK
Clockin => Counter[20].CLK
Clockin => Counter[19].CLK
Clockin => Counter[18].CLK
Clockin => Counter[17].CLK
Clockin => Counter[16].CLK
Clockin => Counter[15].CLK
Clockin => Counter[14].CLK
Clockin => Counter[13].CLK
Clockin => Counter[12].CLK
Clockin => Counter[11].CLK
Clockin => Counter[10].CLK
Clockin => Counter[9].CLK
Clockin => Counter[8].CLK
Clockin => Counter[7].CLK
Clockin => Counter[6].CLK
Clockin => Counter[5].CLK
Clockin => Counter[4].CLK
Clockin => Counter[3].CLK
Clockin => Counter[2].CLK
Clockin => Counter[1].CLK
Clockin => Counter[0].CLK
Clockin => Temp1.CLK
Clockin => Counter[25].CLK
Clockin => Temp2.CLK
ClockOut <= ClockOut~0.DB_MAX_OUTPUT_PORT_TYPE