sled.tan.qmsg

很多vhdl例程代码

{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clock register int_div:inst1\|Counter\[25\] register int_div:inst1\|Counter\[25\] 1.64 ns " "Info: Minimum slack time is 1.64 ns for clock \"clock\" between source register \"int_div:inst1\|Counter\[25\]\" and destination register \"int_div:inst1\|Counter\[25\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.431 ns + Shortest register register " "Info: + Shortest register to register delay is 1.431 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst1\|Counter\[25\] 1 REG LC_X9_Y11_N8 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y11_N8; Fanout = 3; REG Node = 'int_div:inst1\|Counter\[25\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "" { int_div:inst1|Counter[25] } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.442 ns) 0.940 ns int_div:inst1\|add~476 2 COMB LC_X9_Y11_N7 1 " "Info: 2: + IC(0.498 ns) + CELL(0.442 ns) = 0.940 ns; Loc. = LC_X9_Y11_N7; Fanout = 1; COMB Node = 'int_div:inst1\|add~476'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "0.940 ns" { int_div:inst1|Counter[25] int_div:inst1|add~476 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.309 ns) 1.431 ns int_div:inst1\|Counter\[25\] 3 REG LC_X9_Y11_N8 3 " "Info: 3: + IC(0.182 ns) + CELL(0.309 ns) = 1.431 ns; Loc. = LC_X9_Y11_N8; Fanout = 3; REG Node = 'int_div:inst1\|Counter\[25\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "0.491 ns" { int_div:inst1|add~476 int_div:inst1|Counter[25] } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.751 ns 52.48 % " "Info: Total cell delay = 0.751 ns ( 52.48 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.680 ns 47.52 % " "Info: Total interconnect delay = 0.680 ns ( 47.52 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "1.431 ns" { int_div:inst1|Counter[25] int_div:inst1|add~476 int_div:inst1|Counter[25] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.431 ns" { int_div:inst1|Counter[25] int_div:inst1|add~476 int_div:inst1|Counter[25] } { 0.0ns 0.498ns 0.182ns } { 0.0ns 0.442ns 0.309ns } } }  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clock 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clock\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clock 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clock\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.925 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_28 28 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 28; CLK Node = 'clock'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "" { clock } "NODE_NAME" } "" } } { "sled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.bdf" { { 72 -96 72 88 "clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns int_div:inst1\|Counter\[25\] 2 REG LC_X9_Y11_N8 3 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X9_Y11_N8; Fanout = 3; REG Node = 'int_div:inst1\|Counter\[25\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "1.456 ns" { clock int_div:inst1|Counter[25] } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.53 % " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns 25.47 % " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "2.925 ns" { clock int_div:inst1|Counter[25] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clock clock~out0 int_div:inst1|Counter[25] } { 0.0ns 0.0ns 0.745ns } { 0.0ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.925 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to source register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_28 28 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 28; CLK Node = 'clock'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "" { clock } "NODE_NAME" } "" } } { "sled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.bdf" { { 72 -96 72 88 "clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns int_div:inst1\|Counter\[25\] 2 REG LC_X9_Y11_N8 3 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X9_Y11_N8; Fanout = 3; REG Node = 'int_div:inst1\|Counter\[25\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "1.456 ns"