sled.tan.qmsg

很多vhdl例程代码

{ "Info" "ITDB_FULL_SLACK_RESULT" "clock register int_div:inst1\|Counter\[2\] register int_div:inst1\|Counter\[11\] 13.935 ns " "Info: Slack time is 13.935 ns for clock \"clock\" between source register \"int_div:inst1\|Counter\[2\]\" and destination register \"int_div:inst1\|Counter\[11\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "164.88 MHz 6.065 ns " "Info: Fmax is 164.88 MHz (period= 6.065 ns)" {  } {  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "19.739 ns + Largest register register " "Info: + Largest register to register requirement is 19.739 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.000 ns + " "Info: + Setup relationship between source and destination is 20.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 20.000 ns " "Info: + Latch edge is 20.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clock 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clock\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clock 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clock\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.954 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_28 28 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 28; CLK Node = 'clock'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "" { clock } "NODE_NAME" } "" } } { "sled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.bdf" { { 72 -96 72 88 "clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns int_div:inst1\|Counter\[11\] 2 REG LC_X10_Y13_N6 5 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X10_Y13_N6; Fanout = 5; REG Node = 'int_div:inst1\|Counter\[11\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "1.485 ns" { clock int_div:inst1|Counter[11] } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "2.954 ns" { clock int_div:inst1|Counter[11] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clock clock~out0 int_div:inst1|Counter[11] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.954 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_28 28 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 28; CLK Node = 'clock'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "" { clock } "NODE_NAME" } "" } } { "sled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/sled.bdf" { { 72 -96 72 88 "clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns int_div:inst1\|Counter\[2\] 2 REG LC_X8_Y13_N2 4 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X8_Y13_N2; Fanout = 4; REG Node = 'int_div:inst1\|Counter\[2\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "1.485 ns" { clock int_div:inst1|Counter[2] } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "2.954 ns" { clock int_div:inst1|Counter[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clock clock~out0 int_div:inst1|Counter[2] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "2.954 ns" { clock int_div:inst1|Counter[11] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clock clock~out0 int_div:inst1|Counter[11] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "2.954 ns" { clock int_div:inst1|Counter[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clock clock~out0 int_div:inst1|Counter[2] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/int_div.vhd" 37 -1 0 } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "2.954 ns" { clock int_div:inst1|Counter[11] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clock clock~out0 int_div:inst1|Counter[11] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "2.954 ns" { clock int_div:inst1|Counter[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clock clock~out0 int_div:inst1|Counter[2] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.804 ns - Longest register register " "Info: - Longest register to register delay is 5.804 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst1\|Counter\[2\] 1 REG LC_X8_Y13_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y13_N2; Fanout = 4; REG Node = 'int_div:inst1\|Counter\[2\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "" { int_div:inst1|Counter[2] } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.538 ns) + CELL(0.590 ns) 1.128 ns int_div:inst1\|reduce_nor~321 2 COMB LC_X8_Y13_N6 1 " "Info: 2: + IC(0.538 ns) + CELL(0.590 ns) = 1.128 ns; Loc. = LC_X8_Y13_N6; Fanout = 1; COMB Node = 'int_div:inst1\|reduce_nor~321'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "1.128 ns" { int_div:inst1|Counter[2] int_div:inst1|reduce_nor~321 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.701 ns) + CELL(0.590 ns) 2.419 ns int_div:inst1\|reduce_nor~323 3 COMB LC_X9_Y13_N1 1 " "Info: 3: + IC(0.701 ns) + CELL(0.590 ns) = 2.419 ns; Loc. = LC_X9_Y13_N1; Fanout = 1; COMB Node = 'int_div:inst1\|reduce_nor~323'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "1.291 ns" { int_div:inst1|reduce_nor~321 int_div:inst1|reduce_nor~323 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.250 ns) + CELL(0.292 ns) 3.961 ns int_div:inst1\|reduce_nor~0 4 COMB LC_X10_Y12_N4 11 " "Info: 4: + IC(1.250 ns) + CELL(0.292 ns) = 3.961 ns; Loc. = LC_X10_Y12_N4; Fanout = 11; COMB Node = 'int_div:inst1\|reduce_nor~0'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "1.542 ns" { int_div:inst1|reduce_nor~323 int_div:inst1|reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.236 ns) + CELL(0.607 ns) 5.804 ns int_div:inst1\|Counter\[11\] 5 REG LC_X10_Y13_N6 5 " "Info: 5: + IC(1.236 ns) + CELL(0.607 ns) = 5.804 ns; Loc. = LC_X10_Y13_N6; Fanout = 5; REG Node = 'int_div:inst1\|Counter\[11\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "1.843 ns" { int_div:inst1|reduce_nor~0 int_div:inst1|Counter[11] } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.079 ns 35.82 % " "Info: Total cell delay = 2.079 ns ( 35.82 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.725 ns 64.18 % " "Info: Total interconnect delay = 3.725 ns ( 64.18 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "5.804 ns" { int_div:inst1|Counter[2] int_div:inst1|reduce_nor~321 int_div:inst1|reduce_nor~323 int_div:inst1|reduce_nor~0 int_div:inst1|Counter[11] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.804 ns" { int_div:inst1|Counter[2] int_div:inst1|reduce_nor~321 int_div:inst1|reduce_nor~323 int_div:inst1|reduce_nor~0 int_div:inst1|Counter[11] } { 0.000ns 0.538ns 0.701ns 1.250ns 1.236ns } { 0.000ns 0.590ns 0.590ns 0.292ns 0.607ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "2.954 ns" { clock int_div:inst1|Counter[11] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clock clock~out0 int_div:inst1|Counter[11] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "2.954 ns" { clock int_div:inst1|Counter[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clock clock~out0 int_div:inst1|Counter[2] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "5.804 ns" { int_div:inst1|Counter[2] int_div:inst1|reduce_nor~321 int_div:inst1|reduce_nor~323 int_div:inst1|reduce_nor~0 int_div:inst1|Counter[11] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.804 ns" { int_div:inst1|Counter[2] int_div:inst1|reduce_nor~321 int_div:inst1|reduce_nor~323 int_div:inst1|reduce_nor~0 int_div:inst1|Counter[11] } { 0.000ns 0.538ns 0.701ns 1.250ns 1.236ns } { 0.000ns 0.590ns 0.590ns 0.292ns 0.607ns } } }  } 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "int_div:inst1\|ClockOut register counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[3\] register counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[3\] 1.157 ns " "Info: Minimum slack time is 1.157 ns for clock \"int_div:inst1\|ClockOut\" between source register \"counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[3\]\" and destination register \"counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[3\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.948 ns + Shortest register register " "Info: + Shortest register to register delay is 0.948 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[3\] 1 REG LC_X34_Y16_N3 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y16_N3; Fanout = 8; REG Node = 'counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[3\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "" { counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "db/cntr_cs6.tdf" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/cntr_cs6.tdf" 70 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.639 ns) + CELL(0.309 ns) 0.948 ns counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[3\] 2 REG LC_X34_Y16_N3 8 " "Info: 2: + IC(0.639 ns) + CELL(0.309 ns) = 0.948 ns; Loc. = LC_X34_Y16_N3; Fanout = 8; REG Node = 'counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[3\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "0.948 ns" { counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "db/cntr_cs6.tdf" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/cntr_cs6.tdf" 70 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns 32.59 % " "Info: Total cell delay = 0.309 ns ( 32.59 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.639 ns 67.41 % " "Info: Total interconnect delay = 0.639 ns ( 67.41 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "0.948 ns" { counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.948 ns" { counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } { 0.0ns 0.639ns } { 0.0ns 0.309ns } } }  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination int_div:inst1\|ClockOut 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"int_div:inst1\|ClockOut\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source int_div:inst1\|ClockOut 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"int_div:inst1\|ClockOut\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "int_div:inst1\|ClockOut destination 4.210 ns + Longest register " "Info: + Longest clock path from clock \"int_div:inst1\|ClockOut\" to destination register is 4.210 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst1\|ClockOut 1 CLK LC_X8_Y10_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y10_N5; Fanout = 4; CLK Node = 'int_div:inst1\|ClockOut'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "" { int_div:inst1|ClockOut } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/int_div.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.499 ns) + CELL(0.711 ns) 4.210 ns counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[3\] 2 REG LC_X34_Y16_N3 8 " "Info: 2: + IC(3.499 ns) + CELL(0.711 ns) = 4.210 ns; Loc. = LC_X34_Y16_N3; Fanout = 8; REG Node = 'counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[3\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "db/cntr_cs6.tdf" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/cntr_cs6.tdf" 70 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 16.89 % " "Info: Total cell delay = 0.711 ns ( 16.89 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.499 ns 83.11 % " "Info: Total interconnect delay = 3.499 ns ( 83.11 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } { 0.0ns 3.499ns } { 0.0ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "int_div:inst1\|ClockOut source 4.210 ns - Shortest register " "Info: - Shortest clock path from clock \"int_div:inst1\|ClockOut\" to source register is 4.210 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst1\|ClockOut 1 CLK LC_X8_Y10_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y10_N5; Fanout = 4; CLK Node = 'int_div:inst1\|ClockOut'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "" { int_div:inst1|ClockOut } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/int_div.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.499 ns) + CELL(0.711 ns) 4.210 ns counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[3\] 2 REG LC_X34_Y16_N3 8 " "Info: 2: + IC(3.499 ns) + CELL(0.711 ns) = 4.210 ns; Loc. = LC_X34_Y16_N3; Fanout = 8; REG Node = 'counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[3\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "db/cntr_cs6.tdf" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/cntr_cs6.tdf" 70 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 16.89 % " "Info: Total cell delay = 0.711 ns ( 16.89 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.499 ns 83.11 % " "Info: Total interconnect delay = 3.499 ns ( 83.11 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } { 0.0ns 3.499ns } { 0.0ns 0.711ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } { 0.0ns 3.499ns } { 0.0ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } { 0.0ns 3.499ns } { 0.0ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "db/cntr_cs6.tdf" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/cntr_cs6.tdf" 70 8 0 } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "db/cntr_cs6.tdf" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/cntr_cs6.tdf" 70 8 0 } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } { 0.0ns 3.499ns } { 0.0ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } { 0.0ns 3.499ns } { 0.0ns 0.711ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "0.948 ns" { counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.948 ns" { counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } { 0.0ns 0.639ns } { 0.0ns 0.309ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } { 0.0ns 3.499ns } { 0.0ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } { 0.0ns 3.499ns } { 0.0ns 0.711ns } } }  } 0}