sled.tan.qmsg

很多vhdl例程代码

{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off sled -c sled --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sled -c sled --timing_analysis_only" {  } {  } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "int_div:inst1\|ClockOut register counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[1\] register counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[3\] 17.694 ns " "Info: Slack time is 17.694 ns for clock \"int_div:inst1\|ClockOut\" between source register \"counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[1\]\" and destination register \"counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[3\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT_RESTRICTED" "275.03 MHz " "Info: Fmax is restricted to 275.03 MHz due to tcl and tch limits" {  } {  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "19.739 ns + Largest register register " "Info: + Largest register to register requirement is 19.739 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.000 ns + " "Info: + Setup relationship between source and destination is 20.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 20.000 ns " "Info: + Latch edge is 20.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination int_div:inst1\|ClockOut 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"int_div:inst1\|ClockOut\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source int_div:inst1\|ClockOut 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"int_div:inst1\|ClockOut\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "int_div:inst1\|ClockOut destination 4.210 ns + Shortest register " "Info: + Shortest clock path from clock \"int_div:inst1\|ClockOut\" to destination register is 4.210 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst1\|ClockOut 1 CLK LC_X8_Y10_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y10_N5; Fanout = 4; CLK Node = 'int_div:inst1\|ClockOut'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "" { int_div:inst1|ClockOut } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/int_div.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.499 ns) + CELL(0.711 ns) 4.210 ns counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[3\] 2 REG LC_X34_Y16_N3 8 " "Info: 2: + IC(3.499 ns) + CELL(0.711 ns) = 4.210 ns; Loc. = LC_X34_Y16_N3; Fanout = 8; REG Node = 'counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[3\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "db/cntr_cs6.tdf" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/cntr_cs6.tdf" 70 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 16.89 % " "Info: Total cell delay = 0.711 ns ( 16.89 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.499 ns 83.11 % " "Info: Total interconnect delay = 3.499 ns ( 83.11 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } { 0.000ns 3.499ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "int_div:inst1\|ClockOut source 4.210 ns - Longest register " "Info: - Longest clock path from clock \"int_div:inst1\|ClockOut\" to source register is 4.210 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst1\|ClockOut 1 CLK LC_X8_Y10_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y10_N5; Fanout = 4; CLK Node = 'int_div:inst1\|ClockOut'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "" { int_div:inst1|ClockOut } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/int_div.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.499 ns) + CELL(0.711 ns) 4.210 ns counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[1\] 2 REG LC_X34_Y16_N1 10 " "Info: 2: + IC(3.499 ns) + CELL(0.711 ns) = 4.210 ns; Loc. = LC_X34_Y16_N1; Fanout = 10; REG Node = 'counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[1\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "db/cntr_cs6.tdf" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/cntr_cs6.tdf" 70 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 16.89 % " "Info: Total cell delay = 0.711 ns ( 16.89 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.499 ns 83.11 % " "Info: Total interconnect delay = 3.499 ns ( 83.11 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] } { 0.000ns 3.499ns } { 0.000ns 0.711ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } { 0.000ns 3.499ns } { 0.000ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] } { 0.000ns 3.499ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "db/cntr_cs6.tdf" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/cntr_cs6.tdf" 70 8 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "db/cntr_cs6.tdf" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/cntr_cs6.tdf" 70 8 0 } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } { 0.000ns 3.499ns } { 0.000ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] } { 0.000ns 3.499ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.045 ns - Longest register register " "Info: - Longest register to register delay is 2.045 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[1\] 1 REG LC_X34_Y16_N1 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y16_N1; Fanout = 10; REG Node = 'counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[1\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "" { counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "db/cntr_cs6.tdf" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/cntr_cs6.tdf" 70 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.603 ns) + CELL(0.575 ns) 1.178 ns counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|counter_cella1~COUTCOUT1 2 COMB LC_X34_Y16_N1 2 " "Info: 2: + IC(0.603 ns) + CELL(0.575 ns) = 1.178 ns; Loc. = LC_X34_Y16_N1; Fanout = 2; COMB Node = 'counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|counter_cella1~COUTCOUT1'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "1.178 ns" { counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|counter_cella1~COUTCOUT1 } "NODE_NAME" } "" } } { "db/cntr_cs6.tdf" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/cntr_cs6.tdf" 39 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.258 ns counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|counter_cella2~COUTCOUT1_1 3 COMB LC_X34_Y16_N2 1 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.258 ns; Loc. = LC_X34_Y16_N2; Fanout = 1; COMB Node = 'counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|counter_cella2~COUTCOUT1_1'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "0.080 ns" { counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|counter_cella1~COUTCOUT1 counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|counter_cella2~COUTCOUT1_1 } "NODE_NAME" } "" } } { "db/cntr_cs6.tdf" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/cntr_cs6.tdf" 47 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.787 ns) 2.045 ns counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[3\] 4 REG LC_X34_Y16_N3 8 " "Info: 4: + IC(0.000 ns) + CELL(0.787 ns) = 2.045 ns; Loc. = LC_X34_Y16_N3; Fanout = 8; REG Node = 'counter:inst2\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[3\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "0.787 ns" { counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|counter_cella2~COUTCOUT1_1 counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "db/cntr_cs6.tdf" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/cntr_cs6.tdf" 70 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.442 ns 70.51 % " "Info: Total cell delay = 1.442 ns ( 70.51 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.603 ns 29.49 % " "Info: Total interconnect delay = 0.603 ns ( 29.49 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "2.045 ns" { counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|counter_cella1~COUTCOUT1 counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|counter_cella2~COUTCOUT1_1 counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.045 ns" { counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|counter_cella1~COUTCOUT1 counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|counter_cella2~COUTCOUT1_1 counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } { 0.000ns 0.603ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.787ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } { 0.000ns 3.499ns } { 0.000ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.210 ns" { int_div:inst1|ClockOut counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] } { 0.000ns 3.499ns } { 0.000ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled_cmp.qrpt" Compiler "sled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/db/sled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_4_sled/" "" "2.045 ns" { counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|counter_cella1~COUTCOUT1 counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|counter_cella2~COUTCOUT1_1 counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.045 ns" { counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|counter_cella1~COUTCOUT1 counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|counter_cella2~COUTCOUT1_1 counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } { 0.000ns 0.603ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.787ns } } }  } 0}