sled.tan.rpt

很多vhdl例程代码

; Timing Models                                         ; Final              ;      ;                        ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;                        ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;                        ;             ;
; Number of paths to report                             ; 200                ;      ;                        ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;                        ;             ;
; Use Fast Timing Models                                ; Off                ;      ;                        ;             ;
; Report IO Paths Separately                            ; Off                ;      ;                        ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;                        ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;                        ;             ;
; Cut off read during write signal paths                ; On                 ;      ;                        ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;                        ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;                        ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;                        ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;                        ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;                        ;             ;
; Enable Clock Latency                                  ; Off                ;      ;                        ;             ;
; Clock Settings                                        ; clock              ;      ; clock                  ;             ;
; Clock Settings                                        ; clockout           ;      ; int_div:inst1|ClockOut ;             ;
; Clock Settings                                        ; temp               ;      ; int_div:inst1|Temp1    ;             ;
; Clock Settings                                        ; temp               ;      ; int_div:inst1|Temp2    ;             ;
+-------------------------------------------------------+--------------------+------+------------------------+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                         ;
+------------------------+--------------------+---------------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name        ; Clock Setting Name ; Type          ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+------------------------+--------------------+---------------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; int_div:inst1|ClockOut ; clockout           ; Internal Node ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
; int_div:inst1|Temp2    ; temp               ; Internal Node ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
; int_div:inst1|Temp1    ; temp               ; Internal Node ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
; clock                  ; clock              ; User Pin      ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+------------------------+--------------------+---------------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'int_div:inst1|ClockOut'                                                                                                                                                                                                                                                                                                                                   ;
+-----------+-----------------------------------------------+-----------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+------------------------+------------------------+-----------------------------+---------------------------+-------------------------+
; Slack     ; Actual fmax (period)                          ; From                                                                              ; To                                                                                ; From Clock             ; To Clock               ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------+-----------------------------------------------+-----------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+------------------------+------------------------+-----------------------------+---------------------------+-------------------------+
; 17.694 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] ; counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] ; int_div:inst1|ClockOut ; int_div:inst1|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 2.045 ns                ;
; 17.722 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[0] ; counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] ; int_div:inst1|ClockOut ; int_div:inst1|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 2.017 ns                ;
; 17.774 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] ; counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[2] ; int_div:inst1|ClockOut ; int_div:inst1|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 1.965 ns                ;
; 17.774 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[2] ; counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] ; int_div:inst1|ClockOut ; int_div:inst1|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 1.965 ns                ;
; 17.802 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[0] ; counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[2] ; int_div:inst1|ClockOut ; int_div:inst1|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 1.937 ns                ;
; 17.882 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[0] ; counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] ; int_div:inst1|ClockOut ; int_div:inst1|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 1.857 ns                ;
; 18.398 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] ; counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] ; int_div:inst1|ClockOut ; int_div:inst1|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 1.341 ns                ;
; 18.398 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[2] ; counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[2] ; int_div:inst1|ClockOut ; int_div:inst1|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 1.341 ns                ;
; 18.494 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[0] ; counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[0] ; int_div:inst1|ClockOut ; int_div:inst1|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 1.245 ns                ;
; 18.791 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] ; counter:inst2|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] ; int_div:inst1|ClockOut ; int_div:inst1|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 0.948 ns                ;
+-----------+-----------------------------------------------+-----------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+------------------------+------------------------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock'                                                                                                                                                                                                                                              ;
+-----------------------------------------+-----------------------------------------------------+---------------------------+---------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                      ; To                        ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------+---------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; 13.935 ns                               ; 164.88 MHz ( period = 6.065 ns )                    ; int_div:inst1|Counter[2]  ; int_div:inst1|Counter[11] ; clock      ; clock    ; 20.000 ns                   ; 19.739 ns                 ; 5.804 ns                ;
; 13.951 ns                               ; 165.32 MHz ( period = 6.049 ns )                    ; int_div:inst1|Counter[7]  ; int_div:inst1|Counter[11] ; clock      ; clock    ; 20.000 ns                   ; 19.739 ns                 ; 5.788 ns                ;