dled.map.qmsg

来自「很多vhdl例程代码」· QMSG 代码 · 共 18 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1.04 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1.04 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Sep 15 16:35:50 2006 " "Info: Processing started: Fri Sep 15 16:35:50 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dled -c dled " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dled -c dled" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "scan_led.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file scan_led.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 scan_led-one " "Info: Found design unit 1: scan_led-one" {  } { { "scan_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/scan_led.vhd" 36 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 scan_led " "Info: Found entity 1: scan_led" {  } { { "scan_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/scan_led.vhd" 27 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dled.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file dled.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 dled " "Info: Found entity 1: dled" {  } { { "dled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/dled.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "dled " "Info: Elaborating entity \"dled\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scan_led scan_led:inst1 " "Info: Elaborating entity \"scan_led\" for hierarchy \"scan_led:inst1\"" {  } { { "dled.bdf" "inst1" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/dled.bdf" { { 72 328 464 168 "inst1" "" } } } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "int_div.vhd 2 1 " "Info: Using design file int_div.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 int_div-Devider " "Info: Found design unit 1: int_div-Devider" {  } { { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/int_div.vhd" 36 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 int_div " "Info: Found entity 1: int_div" {  } { { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/int_div.vhd" 27 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "int_div int_div:inst " "Info: Elaborating entity \"int_div\" for hierarchy \"int_div:inst\"" {  } { { "dled.bdf" "inst" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/dled.bdf" { { 72 104 240 168 "inst" "" } } } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "CONSTANT_3V8.vhd 4 2 " "Info: Using design file CONSTANT_3V8.vhd, which is not specified as a design file for the current project, but contains definitions for 4 design units and 2 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CONSTANT_3V8_lpm_constant_3v8-RTL " "Info: Found design unit 1: CONSTANT_3V8_lpm_constant_3v8-RTL" {  } { { "CONSTANT_3V8.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/CONSTANT_3V8.vhd" 47 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 CONSTANT_3V8-RTL " "Info: Found design unit 2: CONSTANT_3V8-RTL" {  } { { "CONSTANT_3V8.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/CONSTANT_3V8.vhd" 70 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 CONSTANT_3V8_lpm_constant_3v8 " "Info: Found entity 1: CONSTANT_3V8_lpm_constant_3v8" {  } { { "CONSTANT_3V8.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/CONSTANT_3V8.vhd" 40 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 CONSTANT_3V8 " "Info: Found entity 2: CONSTANT_3V8" {  } { { "CONSTANT_3V8.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/CONSTANT_3V8.vhd" 62 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CONSTANT_3V8 CONSTANT_3V8:inst4 " "Info: Elaborating entity \"CONSTANT_3V8\" for hierarchy \"CONSTANT_3V8:inst4\"" {  } { { "dled.bdf" "inst4" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/dled.bdf" { { 200 120 224 248 "inst4" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CONSTANT_3V8_lpm_constant_3v8 CONSTANT_3V8:inst4\|CONSTANT_3V8_lpm_constant_3v8:CONSTANT_3V8_lpm_constant_3v8_component " "Info: Elaborating entity \"CONSTANT_3V8_lpm_constant_3v8\" for hierarchy \"CONSTANT_3V8:inst4\|CONSTANT_3V8_lpm_constant_3v8:CONSTANT_3V8_lpm_constant_3v8_component\"" {  } { { "CONSTANT_3V8.vhd" "CONSTANT_3V8_lpm_constant_3v8_component" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/CONSTANT_3V8.vhd" 87 -1 0 } }  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "scan_led:inst1\|dig_r\[0\] scan_led:inst1\|disp_dat\[3\] " "Info: Duplicate register \"scan_led:inst1\|dig_r\[0\]\" merged to single register \"scan_led:inst1\|disp_dat\[3\]\", power-up level changed" {  } { { "scan_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/scan_led.vhd" 38 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "scan_led:inst1\|count\[0\] scan_led:inst1\|disp_dat\[0\] " "Info: Duplicate register \"scan_led:inst1\|count\[0\]\" merged to single register \"scan_led:inst1\|disp_dat\[0\]\"" {  } { { "scan_led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/scan_led.vhd" 40 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "seg\[7\] VCC " "Warning: Pin \"seg\[7\]\" stuck at VCC" {  } { { "dled.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_5_dled/dled.bdf" { { 112 504 680 128 "seg\[7..0\]" "" } } } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "82 " "Info: Implemented 82 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "65 " "Info: Implemented 65 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 15 16:35:52 2006 " "Info: Processing ended: Fri Sep 15 16:35:52 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}