dled.tan.rpt

来自「很多vhdl例程代码」· RPT 代码 · 共 343 行 · 第 1/5 页

; Cut off read during write signal paths                ; On                 ;      ;                       ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;                       ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;                       ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;                       ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;                       ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;                       ;             ;
; Enable Clock Latency                                  ; Off                ;      ;                       ;             ;
; Clock Settings                                        ; clock              ;      ; clock_48M             ;             ;
; Clock Settings                                        ; clockout           ;      ; int_div:inst|ClockOut ;             ;
; Clock Settings                                        ; temp               ;      ; int_div:inst|Temp1    ;             ;
; Clock Settings                                        ; temp               ;      ; int_div:inst|Temp2    ;             ;
+-------------------------------------------------------+--------------------+------+-----------------------+-------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                        ;
+-----------------------+--------------------+---------------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name       ; Clock Setting Name ; Type          ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------------+--------------------+---------------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; int_div:inst|ClockOut ; clockout           ; Internal Node ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
; int_div:inst|Temp2    ; temp               ; Internal Node ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
; int_div:inst|Temp1    ; temp               ; Internal Node ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
; clock_48M             ; clock              ; User Pin      ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------------+--------------------+---------------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'int_div:inst|ClockOut'                                                                                                                                                                                                                    ;
+-----------+-----------------------------------------------+----------------------------+----------------------------+-----------------------+-----------------------+-----------------------------+---------------------------+-------------------------+
; Slack     ; Actual fmax (period)                          ; From                       ; To                         ; From Clock            ; To Clock              ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------+-----------------------------------------------+----------------------------+----------------------------+-----------------------+-----------------------+-----------------------------+---------------------------+-------------------------+
; 16.851 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|disp_dat[0] ; scan_led:inst1|count[2]    ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 2.888 ns                ;
; 17.560 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|count[1]    ; scan_led:inst1|count[2]    ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 2.179 ns                ;
; 17.873 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|disp_dat[0] ; scan_led:inst1|count[1]    ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 1.866 ns                ;
; 17.905 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|count[2]    ; scan_led:inst1|disp_dat[3] ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.760 ns                 ; 1.855 ns                ;
; 18.005 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|disp_dat[0] ; scan_led:inst1|disp_dat[3] ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.760 ns                 ; 1.755 ns                ;
; 18.050 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|count[2]    ; scan_led:inst1|dig_r[3]    ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 1.689 ns                ;
; 18.051 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|count[2]    ; scan_led:inst1|dig_r[7]    ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 1.688 ns                ;
; 18.052 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|count[2]    ; scan_led:inst1|dig_r[4]    ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 1.687 ns                ;
; 18.055 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|count[2]    ; scan_led:inst1|dig_r[6]    ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 1.684 ns                ;
; 18.056 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|count[2]    ; scan_led:inst1|disp_dat[2] ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 1.683 ns                ;
; 18.059 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|count[2]    ; scan_led:inst1|dig_r[1]    ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 1.680 ns                ;
; 18.060 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|count[2]    ; scan_led:inst1|dig_r[2]    ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 1.679 ns                ;
; 18.061 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|count[2]    ; scan_led:inst1|dig_r[5]    ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 1.678 ns                ;
; 18.187 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|count[1]    ; scan_led:inst1|disp_dat[3] ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.760 ns                 ; 1.573 ns                ;
; 18.195 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|count[1]    ; scan_led:inst1|dig_r[2]    ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 1.544 ns                ;
; 18.195 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|count[1]    ; scan_led:inst1|dig_r[1]    ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 1.544 ns                ;
; 18.196 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|count[1]    ; scan_led:inst1|dig_r[5]    ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 1.543 ns                ;
; 18.196 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|count[1]    ; scan_led:inst1|dig_r[3]    ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 1.543 ns                ;
; 18.197 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|count[1]    ; scan_led:inst1|dig_r[7]    ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 1.542 ns                ;
; 18.198 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|count[1]    ; scan_led:inst1|dig_r[4]    ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 1.541 ns                ;
; 18.199 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|count[1]    ; scan_led:inst1|disp_dat[1] ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 1.540 ns                ;
; 18.199 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|count[1]    ; scan_led:inst1|disp_dat[2] ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 1.540 ns                ;
; 18.201 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|count[1]    ; scan_led:inst1|dig_r[6]    ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 1.538 ns                ;
; 18.707 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|count[1]    ; scan_led:inst1|count[1]    ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 1.032 ns                ;
; 18.749 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|disp_dat[0] ; scan_led:inst1|dig_r[3]    ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 0.990 ns                ;
; 18.750 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|disp_dat[0] ; scan_led:inst1|dig_r[7]    ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 0.989 ns                ;
; 18.751 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|disp_dat[0] ; scan_led:inst1|dig_r[4]    ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 0.988 ns                ;
; 18.752 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|disp_dat[0] ; scan_led:inst1|disp_dat[1] ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 0.987 ns                ;
; 18.754 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|disp_dat[0] ; scan_led:inst1|dig_r[6]    ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 0.985 ns                ;
; 18.756 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|disp_dat[0] ; scan_led:inst1|disp_dat[2] ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 0.983 ns                ;
; 18.757 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|disp_dat[0] ; scan_led:inst1|dig_r[2]    ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 0.982 ns                ;
; 18.757 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|disp_dat[0] ; scan_led:inst1|dig_r[1]    ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 0.982 ns                ;
; 18.758 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|disp_dat[0] ; scan_led:inst1|dig_r[5]    ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 0.981 ns                ;
; 18.760 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|disp_dat[0] ; scan_led:inst1|disp_dat[0] ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 0.979 ns                ;
; 18.916 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; scan_led:inst1|count[2]    ; scan_led:inst1|count[2]    ; int_div:inst|ClockOut ; int_div:inst|ClockOut ; 20.000 ns                   ; 19.739 ns                 ; 0.823 ns                ;
+-----------+-----------------------------------------------+----------------------------+----------------------------+-----------------------+-----------------------+-----------------------------+---------------------------+-------------------------+