constant_3v8.vhd
来自「很多vhdl例程代码」· VHDL 代码 · 共 117 行
VHD
117 行
-- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_constant
-- ============================================================
-- File Name: CONSTANT_3V8.vhd
-- Megafunction Name(s):
-- lpm_constant
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 5.0 Build 168 06/22/2005 SP 1.04 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2005 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--lpm_constant CBX_AUTO_BLACKBOX="ON" ENABLE_RUNTIME_MOD="NO" LPM_CVALUE=12345678 LPM_WIDTH=32 result
--VERSION_BEGIN 5.0 cbx_lpm_constant 2004:04:20:17:40:14:SJ cbx_mgl 2005:05:19:13:51:58:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY CONSTANT_3V8_lpm_constant_3v8 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END CONSTANT_3V8_lpm_constant_3v8;
ARCHITECTURE RTL OF CONSTANT_3V8_lpm_constant_3v8 IS
ATTRIBUTE synthesis_clearbox : boolean;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
BEGIN
result <= "00010010001101000101011001111000";
END RTL; --CONSTANT_3V8_lpm_constant_3v8
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY CONSTANT_3V8 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END CONSTANT_3V8;
ARCHITECTURE RTL OF constant_3v8 IS
ATTRIBUTE synthesis_clearbox: boolean;
ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS TRUE;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT CONSTANT_3V8_lpm_constant_3v8
PORT (
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(31 DOWNTO 0);
CONSTANT_3V8_lpm_constant_3v8_component : CONSTANT_3V8_lpm_constant_3v8
PORT MAP (
result => sub_wire0
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: nBit NUMERIC "32"
-- Retrieval info: PRIVATE: Value NUMERIC "305419896"
-- Retrieval info: PRIVATE: Radix NUMERIC "16"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: WIZMAN_OVERRIDE_CBX_GEN_MODE STRING "ON"
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "305419896"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL CONSTANT_3V8.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL CONSTANT_3V8.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL CONSTANT_3V8.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL CONSTANT_3V8.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL CONSTANT_3V8_inst.vhd FALSE
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