dled.map.eqn

很多vhdl例程代码

-- Copyright (C) 1991-2005 Altera Corporation
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-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
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--C1_dig_r[7] is scan_led:inst1|dig_r[7]
--operation mode is normal

C1_dig_r[7]_lut_out = C1_disp_dat[0] # C1_count[1] # C1_count[2];
C1_dig_r[7] = DFFEAS(C1_dig_r[7]_lut_out, B1_ClockOut, VCC, , , , , , );


--C1_dig_r[6] is scan_led:inst1|dig_r[6]
--operation mode is normal

C1_dig_r[6]_lut_out = C1_count[1] # C1_count[2] # !C1_disp_dat[0];
C1_dig_r[6] = DFFEAS(C1_dig_r[6]_lut_out, B1_ClockOut, VCC, , , , , , );


--C1_dig_r[5] is scan_led:inst1|dig_r[5]
--operation mode is normal

C1_dig_r[5]_lut_out = C1_disp_dat[0] # C1_count[2] # !C1_count[1];
C1_dig_r[5] = DFFEAS(C1_dig_r[5]_lut_out, B1_ClockOut, VCC, , , , , , );


--C1_dig_r[4] is scan_led:inst1|dig_r[4]
--operation mode is normal

C1_dig_r[4]_lut_out = C1_count[2] # !C1_count[1] # !C1_disp_dat[0];
C1_dig_r[4] = DFFEAS(C1_dig_r[4]_lut_out, B1_ClockOut, VCC, , , , , , );


--C1_dig_r[3] is scan_led:inst1|dig_r[3]
--operation mode is normal

C1_dig_r[3]_lut_out = C1_disp_dat[0] # C1_count[1] # !C1_count[2];
C1_dig_r[3] = DFFEAS(C1_dig_r[3]_lut_out, B1_ClockOut, VCC, , , , , , );


--C1_dig_r[2] is scan_led:inst1|dig_r[2]
--operation mode is normal

C1_dig_r[2]_lut_out = C1_count[1] # !C1_count[2] # !C1_disp_dat[0];
C1_dig_r[2] = DFFEAS(C1_dig_r[2]_lut_out, B1_ClockOut, VCC, , , , , , );


--C1_dig_r[1] is scan_led:inst1|dig_r[1]
--operation mode is normal

C1_dig_r[1]_lut_out = C1_disp_dat[0] # !C1_count[2] # !C1_count[1];
C1_dig_r[1] = DFFEAS(C1_dig_r[1]_lut_out, B1_ClockOut, VCC, , , , , , );


--C1_disp_dat[3] is scan_led:inst1|disp_dat[3]
--operation mode is normal

C1_disp_dat[3]_lut_out = C1_disp_dat[0] & C1_count[1] & C1_count[2];
C1_disp_dat[3] = DFFEAS(C1_disp_dat[3]_lut_out, B1_ClockOut, VCC, , , , , , );


--C1_disp_dat[0] is scan_led:inst1|disp_dat[0]
--operation mode is normal

C1_disp_dat[0]_lut_out = !C1_disp_dat[0];
C1_disp_dat[0] = DFFEAS(C1_disp_dat[0]_lut_out, B1_ClockOut, VCC, , , , , , );


--C1_disp_dat[1] is scan_led:inst1|disp_dat[1]
--operation mode is normal

C1_disp_dat[1]_lut_out = C1_disp_dat[0] $ C1_count[1];
C1_disp_dat[1] = DFFEAS(C1_disp_dat[1]_lut_out, B1_ClockOut, VCC, , , , , , );


--C1_disp_dat[2] is scan_led:inst1|disp_dat[2]
--operation mode is normal

C1_disp_dat[2]_lut_out = C1_count[2] $ (C1_disp_dat[0] & C1_count[1]);
C1_disp_dat[2] = DFFEAS(C1_disp_dat[2]_lut_out, B1_ClockOut, VCC, , , , , , );


--C1L42 is scan_led:inst1|seg[6]~103
--operation mode is normal

C1L42 = C1_disp_dat[0] & (C1_disp_dat[3] # C1_disp_dat[1] $ C1_disp_dat[2]) # !C1_disp_dat[0] & (C1_disp_dat[1] # C1_disp_dat[2] $ C1_disp_dat[3]);


--C1L32 is scan_led:inst1|seg[5]~104
--operation mode is normal

C1L32 = C1_disp_dat[0] & (C1_disp_dat[3] $ (C1_disp_dat[1] # !C1_disp_dat[2])) # !C1_disp_dat[0] & C1_disp_dat[1] & !C1_disp_dat[2] & !C1_disp_dat[3];


--C1L22 is scan_led:inst1|seg[4]~105
--operation mode is normal

C1L22 = C1_disp_dat[1] & C1_disp_dat[0] & (!C1_disp_dat[3]) # !C1_disp_dat[1] & (C1_disp_dat[2] & (!C1_disp_dat[3]) # !C1_disp_dat[2] & C1_disp_dat[0]);


--C1L12 is scan_led:inst1|seg[3]~106
--operation mode is normal

C1L12 = C1_disp_dat[1] & (C1_disp_dat[0] & C1_disp_dat[2] # !C1_disp_dat[0] & !C1_disp_dat[2] & C1_disp_dat[3]) # !C1_disp_dat[1] & !C1_disp_dat[3] & (C1_disp_dat[0] $ C1_disp_dat[2]);


--C1L02 is scan_led:inst1|seg[2]~107
--operation mode is normal

C1L02 = C1_disp_dat[2] & C1_disp_dat[3] & (C1_disp_dat[1] # !C1_disp_dat[0]) # !C1_disp_dat[2] & !C1_disp_dat[0] & C1_disp_dat[1] & !C1_disp_dat[3];


--C1L91 is scan_led:inst1|seg[1]~108
--operation mode is normal

C1L91 = C1_disp_dat[1] & (C1_disp_dat[0] & (C1_disp_dat[3]) # !C1_disp_dat[0] & C1_disp_dat[2]) # !C1_disp_dat[1] & C1_disp_dat[2] & (C1_disp_dat[0] $ C1_disp_dat[3]);


--C1L81 is scan_led:inst1|seg[0]~109
--operation mode is normal

C1L81 = C1_disp_dat[2] & !C1_disp_dat[1] & (C1_disp_dat[0] $ !C1_disp_dat[3]) # !C1_disp_dat[2] & C1_disp_dat[0] & (C1_disp_dat[1] $ !C1_disp_dat[3]);


--C1_count[1] is scan_led:inst1|count[1]
--operation mode is normal

C1_count[1]_lut_out = !C1_count[1];
C1_count[1] = DFFEAS(C1_count[1]_lut_out, B1_ClockOut, VCC, , C1_disp_dat[0], , , , );


--C1_count[2] is scan_led:inst1|count[2]
--operation mode is normal

C1_count[2]_lut_out = !C1_count[2];
C1_count[2] = DFFEAS(C1_count[2]_lut_out, B1_ClockOut, VCC, , C1L71, , , , );


--B1_Temp1 is int_div:inst|Temp1
--operation mode is normal

B1_Temp1_lut_out = !B1_Temp1;
B1_Temp1 = DFFEAS(B1_Temp1_lut_out, clock_48M, VCC, , B1L45, , , , );


--B1_Temp2 is int_div:inst|Temp2
--operation mode is normal

B1_Temp2_lut_out = !B1_Temp2;
B1_Temp2 = DFFEAS(B1_Temp2_lut_out, !clock_48M, VCC, , B1L85, , , , );


--B1_ClockOut is int_div:inst|ClockOut
--operation mode is normal

B1_ClockOut = B1_Temp1 $ B1_Temp2;


--C1L71 is scan_led:inst1|Mux~261
--operation mode is normal

C1L71 = C1_disp_dat[0] & C1_count[1];


--B1_Counter[14] is int_div:inst|Counter[14]
--operation mode is normal

B1_Counter[14]_lut_out = B1L1;
B1_Counter[14] = DFFEAS(B1_Counter[14]_lut_out, clock_48M, VCC, , , , , , );


--B1_Counter[10] is int_div:inst|Counter[10]
--operation mode is normal

B1_Counter[10]_lut_out = B1L3;
B1_Counter[10] = DFFEAS(B1_Counter[10]_lut_out, clock_48M, VCC, , , , , , );


--B1_Counter[13] is int_div:inst|Counter[13]
--operation mode is normal

B1_Counter[13]_lut_out = B1L5 & !B1L45;
B1_Counter[13] = DFFEAS(B1_Counter[13]_lut_out, clock_48M, VCC, , , , , , );


--B1_Counter[9] is int_div:inst|Counter[9]
--operation mode is normal

B1_Counter[9]_lut_out = B1L7 & !B1L45;
B1_Counter[9] = DFFEAS(B1_Counter[9]_lut_out, clock_48M, VCC, , , , , , );


--B1L05 is int_div:inst|reduce_nor~199
--operation mode is normal

B1L05 = B1_Counter[14] # B1_Counter[10] # !B1_Counter[9] # !B1_Counter[13];


--B1_Counter[7] is int_div:inst|Counter[7]
--operation mode is normal

B1_Counter[7]_lut_out = B1L9 & !B1L45;
B1_Counter[7] = DFFEAS(B1_Counter[7]_lut_out, clock_48M, VCC, , , , , , );


--B1_Counter[5] is int_div:inst|Counter[5]
--operation mode is normal

B1_Counter[5]_lut_out = B1L11;
B1_Counter[5] = DFFEAS(B1_Counter[5]_lut_out, clock_48M, VCC, , , , , , );


--B1_Counter[4] is int_div:inst|Counter[4]
--operation mode is normal

B1_Counter[4]_lut_out = B1L31;
B1_Counter[4] = DFFEAS(B1_Counter[4]_lut_out, clock_48M, VCC, , , , , , );


--B1_Counter[3] is int_div:inst|Counter[3]
--operation mode is normal

B1_Counter[3]_lut_out = B1L51;
B1_Counter[3] = DFFEAS(B1_Counter[3]_lut_out, clock_48M, VCC, , , , , , );


--B1L15 is int_div:inst|reduce_nor~200
--operation mode is normal

B1L15 = B1_Counter[7] # !B1_Counter[3] # !B1_Counter[4] # !B1_Counter[5];


--B1_Counter[2] is int_div:inst|Counter[2]
--operation mode is normal

B1_Counter[2]_lut_out = B1L71;
B1_Counter[2] = DFFEAS(B1_Counter[2]_lut_out, clock_48M, VCC, , , , , , );


--B1_Counter[1] is int_div:inst|Counter[1]
--operation mode is normal

B1_Counter[1]_lut_out = B1L91;
B1_Counter[1] = DFFEAS(B1_Counter[1]_lut_out, clock_48M, VCC, , , , , , );


--B1_Counter[0] is int_div:inst|Counter[0]
--operation mode is normal

B1_Counter[0]_lut_out = B1L12;
B1_Counter[0] = DFFEAS(B1_Counter[0]_lut_out, clock_48M, VCC, , , , , , );


--B1_Counter[15] is int_div:inst|Counter[15]
--operation mode is normal

B1_Counter[15]_lut_out = B1L32 & !B1L45;
B1_Counter[15] = DFFEAS(B1_Counter[15]_lut_out, clock_48M, VCC, , , , , , );


--B1L25 is int_div:inst|reduce_nor~201
--operation mode is normal

B1L25 = !B1_Counter[15] # !B1_Counter[0] # !B1_Counter[1] # !B1_Counter[2];


--B1_Counter[12] is int_div:inst|Counter[12]
--operation mode is normal

B1_Counter[12]_lut_out = B1L42 & !B1L45;
B1_Counter[12] = DFFEAS(B1_Counter[12]_lut_out, clock_48M, VCC, , , , , , );


--B1_Counter[11] is int_div:inst|Counter[11]
--operation mode is normal

B1_Counter[11]_lut_out = B1L62 & !B1L45;
B1_Counter[11] = DFFEAS(B1_Counter[11]_lut_out, clock_48M, VCC, , , , , , );


--B1_Counter[8] is int_div:inst|Counter[8]
--operation mode is normal

B1_Counter[8]_lut_out = B1L82 & !B1L45;
B1_Counter[8] = DFFEAS(B1_Counter[8]_lut_out, clock_48M, VCC, , , , , , );


--B1_Counter[6] is int_div:inst|Counter[6]
--operation mode is normal

B1_Counter[6]_lut_out = B1L03;
B1_Counter[6] = DFFEAS(B1_Counter[6]_lut_out, clock_48M, VCC, , , , , , );


--B1L35 is int_div:inst|reduce_nor~202
--operation mode is normal

B1L35 = B1_Counter[12] & B1_Counter[11] & B1_Counter[8] & B1_Counter[6];


--B1L45 is int_div:inst|reduce_nor~203
--operation mode is normal

B1L45 = !B1L05 & !B1L15 & !B1L25 & B1L35;