led_test.map.qmsg

来自「很多vhdl例程代码」· QMSG 代码 · 共 11 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1.04 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1.04 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Sep 15 13:33:32 2006 " "Info: Processing started: Fri Sep 15 13:33:32 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off led_test -c led_test " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off led_test -c led_test" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "led.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file led.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 led-one " "Info: Found design unit 1: led-one" {  } { { "led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_1_led_test/led.vhd" 31 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 led " "Info: Found entity 1: led" {  } { { "led.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_1_led_test/led.vhd" 25 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "led_test.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file led_test.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 led_test " "Info: Found entity 1: led_test" {  } { { "led_test.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_1_led_test/led_test.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "led_test " "Info: Elaborating entity \"led_test\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "led led:inst " "Info: Elaborating entity \"led\" for hierarchy \"led:inst\"" {  } { { "led_test.bdf" "inst" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_1_led_test/led_test.bdf" { { 64 144 240 160 "inst" "" } } } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "led\[7\] VCC " "Warning: Pin \"led\[7\]\" stuck at VCC" {  } { { "led_test.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_1_led_test/led_test.bdf" { { 88 272 448 104 "led\[7..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "led\[6\] GND " "Warning: Pin \"led\[6\]\" stuck at GND" {  } { { "led_test.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_1_led_test/led_test.bdf" { { 88 272 448 104 "led\[7..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "led\[5\] VCC " "Warning: Pin \"led\[5\]\" stuck at VCC" {  } { { "led_test.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_1_led_test/led_test.bdf" { { 88 272 448 104 "led\[7..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "led\[4\] GND " "Warning: Pin \"led\[4\]\" stuck at GND" {  } { { "led_test.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_1_led_test/led_test.bdf" { { 88 272 448 104 "led\[7..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "led\[3\] VCC " "Warning: Pin \"led\[3\]\" stuck at VCC" {  } { { "led_test.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_1_led_test/led_test.bdf" { { 88 272 448 104 "led\[7..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "led\[2\] GND " "Warning: Pin \"led\[2\]\" stuck at GND" {  } { { "led_test.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_1_led_test/led_test.bdf" { { 88 272 448 104 "led\[7..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "led\[1\] VCC " "Warning: Pin \"led\[1\]\" stuck at VCC" {  } { { "led_test.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_1_led_test/led_test.bdf" { { 88 272 448 104 "led\[7..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "led\[0\] GND " "Warning: Pin \"led\[0\]\" stuck at GND" {  } { { "led_test.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_1_led_test/led_test.bdf" { { 88 272 448 104 "led\[7..0\]" "" } } } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "8 " "Info: Implemented 8 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "0 " "Info: Implemented 0 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 9 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 15 13:33:33 2006 " "Info: Processing ended: Fri Sep 15 13:33:33 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}