led_test.fit.rpt

来自「很多vhdl例程代码」· RPT 代码 · 共 563 行 · 第 1/4 页

; 224      ; 185        ; 2        ; RESERVED_INPUT ;        ;              ;         ; Column I/O ;                 ;
; 225      ; 186        ; 2        ; RESERVED_INPUT ;        ;              ;         ; Column I/O ;                 ;
; 226      ; 187        ; 2        ; RESERVED_INPUT ;        ;              ;         ; Column I/O ;                 ;
; 227      ; 188        ; 2        ; RESERVED_INPUT ;        ;              ;         ; Column I/O ;                 ;
; 228      ; 189        ; 2        ; RESERVED_INPUT ;        ;              ;         ; Column I/O ;                 ;
; 229      ;            ;          ; VCCINT         ; power  ;              ; 1.5V    ; --         ;                 ;
; 230      ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ;
; 231      ;            ; 2        ; VCCIO2         ; power  ;              ; 3.3V    ; --         ;                 ;
; 232      ;            ;          ; GND            ; gnd    ;              ;         ; --         ;                 ;
; 233      ; 190        ; 2        ; RESERVED_INPUT ;        ;              ;         ; Column I/O ;                 ;
; 234      ; 191        ; 2        ; RESERVED_INPUT ;        ;              ;         ; Column I/O ;                 ;
; 235      ; 192        ; 2        ; RESERVED_INPUT ;        ;              ;         ; Column I/O ;                 ;
; 236      ; 193        ; 2        ; RESERVED_INPUT ;        ;              ;         ; Column I/O ;                 ;
; 237      ; 194        ; 2        ; RESERVED_INPUT ;        ;              ;         ; Column I/O ;                 ;
; 238      ; 195        ; 2        ; RESERVED_INPUT ;        ;              ;         ; Column I/O ;                 ;
; 239      ; 196        ; 2        ; RESERVED_INPUT ;        ;              ;         ; Column I/O ;                 ;
; 240      ; 197        ; 2        ; RESERVED_INPUT ;        ;              ;         ; Column I/O ;                 ;
+----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+


+------------------------------------------------------------------+
; Output Pin Default Load For Reported TCO                         ;
+---------------------+-------+------------------------------------+
; I/O Standard        ; Load  ; Termination Resistance             ;
+---------------------+-------+------------------------------------+
; LVTTL               ; 10 pF ; Not Available                      ;
; LVCMOS              ; 10 pF ; Not Available                      ;
; 2.5 V               ; 10 pF ; Not Available                      ;
; 1.8 V               ; 10 pF ; Not Available                      ;
; 1.5 V               ; 10 pF ; Not Available                      ;
; SSTL-3 Class I      ; 30 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
; SSTL-3 Class II     ; 30 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
; SSTL-2 Class I      ; 30 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
; SSTL-2 Class II     ; 30 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
; Differential SSTL-2 ; 30 pF ; (See SSTL-2)                       ;
; 3.3-V PCI           ; 10 pF ; 25 Ohm (Parallel)                  ;
; LVDS                ; 4 pF  ; 100 Ohm (Differential)             ;
; RSDS                ; 0 pF  ; 100 Ohm (Differential)             ;
+---------------------+-------+------------------------------------+
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity                                                                                                                                                     ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |led_test                  ; 0 (0)       ; 0            ; 0           ; 8    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |led_test           ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------+
; Delay Chain Summary                                                             ;
+--------+----------+---------------+---------------+-----------------------+-----+
; Name   ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
+--------+----------+---------------+---------------+-----------------------+-----+
; led[7] ; Output   ; --            ; --            ; --                    ; --  ;
; led[6] ; Output   ; --            ; --            ; --                    ; --  ;
; led[5] ; Output   ; --            ; --            ; --                    ; --  ;
; led[4] ; Output   ; --            ; --            ; --                    ; --  ;
; led[3] ; Output   ; --            ; --            ; --                    ; --  ;
; led[2] ; Output   ; --            ; --            ; --                    ; --  ;
; led[1] ; Output   ; --            ; --            ; --                    ; --  ;
; led[0] ; Output   ; --            ; --            ; --                    ; --  ;
+--------+----------+---------------+---------------+-----------------------+-----+


+-------------------------------------------------+
; Interconnect Usage Summary                      ;
+----------------------------+--------------------+
; Interconnect Resource Type ; Usage              ;
+----------------------------+--------------------+
; C4s                        ; 0 / 16,320 ( 0 % ) ;
; Direct links               ; 0 / 21,944 ( 0 % ) ;
; Global clocks              ; 0 / 8 ( 0 % )      ;
; LAB clocks                 ; 0 / 240 ( 0 % )    ;
; LUT chains                 ; 0 / 5,382 ( 0 % )  ;
; Local interconnects        ; 0 / 21,944 ( 0 % ) ;
; M4K buffers                ; 0 / 720 ( 0 % )    ;
; R4s                        ; 0 / 14,640 ( 0 % ) ;
+----------------------------+--------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1.04 SJ Full Version
    Info: Processing started: Fri Sep 15 13:33:35 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off led_test -c led_test
Info: Selected device EP1C6Q240C8 for design "led_test"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. 
    Info: Device EP1C12Q240C8 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1 MHz
    Info: Not setting a global tsu requirement
    Info: Not setting a global tco requirement
    Info: Not setting a global tpd requirement
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources.
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Warning: The following 8 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
    Info: Pin led[7] has VCC driving its datain port
    Info: Pin led[6] has GND driving its datain port
    Info: Pin led[5] has VCC driving its datain port
    Info: Pin led[4] has GND driving its datain port
    Info: Pin led[3] has VCC driving its datain port
    Info: Pin led[2] has GND driving its datain port
    Info: Pin led[1] has VCC driving its datain port
    Info: Pin led[0] has GND driving its datain port
Info: Quartus II Fitter was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Sep 15 13:33:40 2006
    Info: Elapsed time: 00:00:05