cnt_4b.tan.qmsg

很多vhdl例程代码

{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "int_div:inst14\|ClockOut register cnt_4b:inst\|cnt\[2\] register cnt_4b:inst\|cnt\[2\] 1.38 ns " "Info: Minimum slack time is 1.38 ns for clock \"int_div:inst14\|ClockOut\" between source register \"cnt_4b:inst\|cnt\[2\]\" and destination register \"cnt_4b:inst\|cnt\[2\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.171 ns + Shortest register register " "Info: + Shortest register to register delay is 1.171 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt_4b:inst\|cnt\[2\] 1 REG LC_X34_Y5_N8 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y5_N8; Fanout = 11; REG Node = 'cnt_4b:inst\|cnt\[2\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "" { cnt_4b:inst|cnt[2] } "NODE_NAME" } "" } } { "cnt_4b.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/cnt_4b.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.564 ns) + CELL(0.607 ns) 1.171 ns cnt_4b:inst\|cnt\[2\] 2 REG LC_X34_Y5_N8 11 " "Info: 2: + IC(0.564 ns) + CELL(0.607 ns) = 1.171 ns; Loc. = LC_X34_Y5_N8; Fanout = 11; REG Node = 'cnt_4b:inst\|cnt\[2\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "1.171 ns" { cnt_4b:inst|cnt[2] cnt_4b:inst|cnt[2] } "NODE_NAME" } "" } } { "cnt_4b.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/cnt_4b.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.607 ns 51.84 % " "Info: Total cell delay = 0.607 ns ( 51.84 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.564 ns 48.16 % " "Info: Total interconnect delay = 0.564 ns ( 48.16 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "1.171 ns" { cnt_4b:inst|cnt[2] cnt_4b:inst|cnt[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.171 ns" { cnt_4b:inst|cnt[2] cnt_4b:inst|cnt[2] } { 0.0ns 0.564ns } { 0.0ns 0.607ns } } }  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination int_div:inst14\|ClockOut 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"int_div:inst14\|ClockOut\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source int_div:inst14\|ClockOut 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"int_div:inst14\|ClockOut\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "int_div:inst14\|ClockOut destination 4.160 ns + Longest register " "Info: + Longest clock path from clock \"int_div:inst14\|ClockOut\" to destination register is 4.160 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst14\|ClockOut 1 CLK LC_X8_Y10_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y10_N5; Fanout = 4; CLK Node = 'int_div:inst14\|ClockOut'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "" { int_div:inst14|ClockOut } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/int_div.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.449 ns) + CELL(0.711 ns) 4.160 ns cnt_4b:inst\|cnt\[2\] 2 REG LC_X34_Y5_N8 11 " "Info: 2: + IC(3.449 ns) + CELL(0.711 ns) = 4.160 ns; Loc. = LC_X34_Y5_N8; Fanout = 11; REG Node = 'cnt_4b:inst\|cnt\[2\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[2] } "NODE_NAME" } "" } } { "cnt_4b.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/cnt_4b.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 17.09 % " "Info: Total cell delay = 0.711 ns ( 17.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.449 ns 82.91 % " "Info: Total interconnect delay = 3.449 ns ( 82.91 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[2] } { 0.0ns 3.449ns } { 0.0ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "int_div:inst14\|ClockOut source 4.160 ns - Shortest register " "Info: - Shortest clock path from clock \"int_div:inst14\|ClockOut\" to source register is 4.160 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst14\|ClockOut 1 CLK LC_X8_Y10_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y10_N5; Fanout = 4; CLK Node = 'int_div:inst14\|ClockOut'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "" { int_div:inst14|ClockOut } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/int_div.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.449 ns) + CELL(0.711 ns) 4.160 ns cnt_4b:inst\|cnt\[2\] 2 REG LC_X34_Y5_N8 11 " "Info: 2: + IC(3.449 ns) + CELL(0.711 ns) = 4.160 ns; Loc. = LC_X34_Y5_N8; Fanout = 11; REG Node = 'cnt_4b:inst\|cnt\[2\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[2] } "NODE_NAME" } "" } } { "cnt_4b.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/cnt_4b.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 17.09 % " "Info: Total cell delay = 0.711 ns ( 17.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.449 ns 82.91 % " "Info: Total interconnect delay = 3.449 ns ( 82.91 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[2] } { 0.0ns 3.449ns } { 0.0ns 0.711ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[2] } { 0.0ns 3.449ns } { 0.0ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[2] } { 0.0ns 3.449ns } { 0.0ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "cnt_4b.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/cnt_4b.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "cnt_4b.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/cnt_4b.vhd" 35 -1 0 } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[2] } { 0.0ns 3.449ns } { 0.0ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[2] } { 0.0ns 3.449ns } { 0.0ns 0.711ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "1.171 ns" { cnt_4b:inst|cnt[2] cnt_4b:inst|cnt[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.171 ns" { cnt_4b:inst|cnt[2] cnt_4b:inst|cnt[2] } { 0.0ns 0.564ns } { 0.0ns 0.607ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[2] } { 0.0ns 3.449ns } { 0.0ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[2] } { 0.0ns 3.449ns } { 0.0ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clock_48M register int_div:inst14\|Counter\[25\] register int_div:inst14\|Counter\[25\] 1.652 ns " "Info: Minimum slack time is 1.652 ns for clock \"clock_48M\" between source register \"int_div:inst14\|Counter\[25\]\" and destination register \"int_div:inst14\|Counter\[25\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.443 ns + Sh