cnt_4b.tan.qmsg

很多vhdl例程代码

{ "Info" "ITAN_NO_REG2REG_EXIST" "int_div:inst14\|Temp1 " "Info: No valid register-to-register data paths exist for clock \"int_div:inst14\|Temp1\"" {  } {  } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "clock_48M register int_div:inst14\|Counter\[10\] register int_div:inst14\|Counter\[11\] 12.805 ns " "Info: Slack time is 12.805 ns for clock \"clock_48M\" between source register \"int_div:inst14\|Counter\[10\]\" and destination register \"int_div:inst14\|Counter\[11\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "138.99 MHz 7.195 ns " "Info: Fmax is 138.99 MHz (period= 7.195 ns)" {  } {  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "19.739 ns + Largest register register " "Info: + Largest register to register requirement is 19.739 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.000 ns + " "Info: + Setup relationship between source and destination is 20.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 20.000 ns " "Info: + Latch edge is 20.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clock_48M 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clock_48M\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clock_48M 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clock_48M\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_48M destination 2.903 ns + Shortest register " "Info: + Shortest clock path from clock \"clock_48M\" to destination register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock_48M 1 CLK PIN_28 28 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 28; CLK Node = 'clock_48M'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "" { clock_48M } "NODE_NAME" } "" } } { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/Block1.bdf" { { 280 -72 96 296 "clock_48M" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns int_div:inst14\|Counter\[11\] 2 REG LC_X13_Y9_N9 5 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X13_Y9_N9; Fanout = 5; REG Node = 'int_div:inst14\|Counter\[11\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "1.434 ns" { clock_48M int_div:inst14|Counter[11] } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.09 % " "Info: Total cell delay = 2.180 ns ( 75.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns 24.91 % " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "2.903 ns" { clock_48M int_div:inst14|Counter[11] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clock_48M clock_48M~out0 int_div:inst14|Counter[11] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock_48M source 2.903 ns - Longest register " "Info: - Longest clock path from clock \"clock_48M\" to source register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock_48M 1 CLK PIN_28 28 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 28; CLK Node = 'clock_48M'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "" { clock_48M } "NODE_NAME" } "" } } { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/Block1.bdf" { { 280 -72 96 296 "clock_48M" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns int_div:inst14\|Counter\[10\] 2 REG LC_X13_Y9_N6 5 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X13_Y9_N6; Fanout = 5; REG Node = 'int_div:inst14\|Counter\[10\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "1.434 ns" { clock_48M int_div:inst14|Counter[10] } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.09 % " "Info: Total cell delay = 2.180 ns ( 75.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns 24.91 % " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "2.903 ns" { clock_48M int_div:inst14|Counter[10] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clock_48M clock_48M~out0 int_div:inst14|Counter[10] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "2.903 ns" { clock_48M int_div:inst14|Counter[11] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clock_48M clock_48M~out0 int_div:inst14|Counter[11] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "2.903 ns" { clock_48M int_div:inst14|Counter[10] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clock_48M clock_48M~out0 int_div:inst14|Counter[10] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/int_div.vhd" 37 -1 0 } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "2.903 ns" { clock_48M int_div:inst14|Counter[11] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clock_48M clock_48M~out0 int_div:inst14|Counter[11] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "2.903 ns" { clock_48M int_div:inst14|Counter[10] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clock_48M clock_48M~out0 int_div:inst14|Counter[10] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.934 ns - Longest register register " "Info: - Longest register to register delay is 6.934 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst14\|Counter\[10\] 1 REG LC_X13_Y9_N6 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y9_N6; Fanout = 5; REG Node = 'int_div:inst14\|Counter\[10\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "" { int_div:inst14|Counter[10] } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.217 ns) + CELL(0.590 ns) 1.807 ns int_div:inst14\|reduce_nor~320 2 COMB LC_X13_Y9_N3 1 " "Info: 2: + IC(1.217 ns) + CELL(0.590 ns) = 1.807 ns; Loc. = LC_X13_Y9_N3; Fanout = 1; COMB Node = 'int_div:inst14\|reduce_nor~320'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "1.807 ns" { int_div:inst14|Counter[10] int_div:inst14|reduce_nor~320 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.709 ns) + CELL(0.590 ns) 3.106 ns int_div:inst14\|reduce_nor~323 3 COMB LC_X12_Y9_N1 1 " "Info: 3: + IC(0.709 ns) + CELL(0.590 ns) = 3.106 ns; Loc. = LC_X12_Y9_N1; Fanout = 1; COMB Node = 'int_div:inst14\|reduce_nor~323'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "1.299 ns" { int_div:inst14|reduce_nor~320 int_div:inst14|reduce_nor~323 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.513 ns) + CELL(0.442 ns) 5.061 ns int_div:inst14\|reduce_nor~0 4 COMB LC_X13_Y8_N5 11 " "Info: 4: + IC(1.513 ns) + CELL(0.442 ns) = 5.061 ns; Loc. = LC_X13_Y8_N5; Fanout = 11; COMB Node = 'int_div:inst14\|reduce_nor~0'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "1.955 ns" { int_div:inst14|reduce_nor~323 int_div:inst14|reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.266 ns) + CELL(0.607 ns) 6.934 ns int_div:inst14\|Counter\[11\] 5 REG LC_X13_Y9_N9 5 " "Info: 5: + IC(1.266 ns) + CELL(0.607 ns) = 6.934 ns; Loc. = LC_X13_Y9_N9; Fanout = 5; REG Node = 'int_div:inst14\|Counter\[11\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "1.873 ns" { int_div:inst14|reduce_nor~0 int_div:inst14|Counter[11] } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.229 ns 32.15 % " "Info: Total cell delay = 2.229 ns ( 32.15 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.705 ns 67.85 % " "Info: Total interconnect delay = 4.705 ns ( 67.85 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "6.934 ns" { int_div:inst14|Counter[10] int_div:inst14|reduce_nor~320 int_div:inst14|reduce_nor~323 int_div:inst14|reduce_nor~0 int_div:inst14|Counter[11] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.934 ns" { int_div:inst14|Counter[10] int_div:inst14|reduce_nor~320 int_div:inst14|reduce_nor~323 int_div:inst14|reduce_nor~0 int_div:inst14|Counter[11] } { 0.000ns 1.217ns 0.709ns 1.513ns 1.266ns } { 0.000ns 0.590ns 0.590ns 0.442ns 0.607ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "2.903 ns" { clock_48M int_div:inst14|Counter[11] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clock_48M clock_48M~out0 int_div:inst14|Counter[11] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "2.903 ns" { clock_48M int_div:inst14|Counter[10] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clock_48M clock_48M~out0 int_div:inst14|Counter[10] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "6.934 ns" { int_div:inst14|Counter[10] int_div:inst14|reduce_nor~320 int_div:inst14|reduce_nor~323 int_div:inst14|reduce_nor~0 int_div:inst14|Counter[11] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.934 ns" { int_div:inst14|Counter[10] int_div:inst14|reduce_nor~320 int_div:inst14|reduce_nor~323 int_div:inst14|reduce_nor~0 int_div:inst14|Counter[11] } { 0.000ns 1.217ns 0.709ns 1.513ns 1.266ns } { 0.000ns 0.590ns 0.590ns 0.442ns 0.607ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "key1 register register inst5 inst5 275.03 MHz Internal " "Info: Clock \"key1\" Internal fmax is restricted to 275.03 MHz between source register \"inst5\" and destination register \"inst5\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.837 ns + Longest register register " "Info: + Longest register to register delay is 0.837 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst5 1 REG LC_X34_Y5_N5 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y5_N5; Fanout = 5; REG Node = 'inst5'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "" { inst5 } "NODE_NAME" } "" } } { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/Block1.bdf" { { 392 88 152 472 "inst5" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.528 ns) + CELL(0.309 ns) 0.837 ns inst5 2 REG LC_X34_Y5_N5 5 " "Info: 2: + IC(0.528 ns) + CELL(0.309 ns) = 0.837 ns; Loc. = LC_X34_Y5_N5; Fanout = 5; REG Node = 'inst5'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "0.837 ns" { inst5 inst5 } "NODE_NAME" } "" } } { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/Block1.bdf" { { 392 88 152 472 "inst5" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns 36.92 % " "Info: Total cell delay = 0.309 ns ( 36.92 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.528 ns 63.08 % " "Info: Total interconnect delay = 0.528 ns ( 63.08 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "0.837 ns" { inst5 inst5 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.837 ns" { inst5 inst5 } { 0.000ns 0.528ns } { 0.000ns 0.309ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "key1 destination 3.515 ns + Shortest register " "Info: + Shortest clock path from clock \"key1\" to destination register is 3.515 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns key1 1 CLK PIN_121 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_121; Fanout = 1; CLK Node = 'key1'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "" { key1 } "NODE_NAME" } "" } } { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/Block1.bdf" { { 424 -88 80 440 "key1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.335 ns) + CELL(0.711 ns) 3.515 ns inst5 2 REG LC_X34_Y5_N5 5 " "Info: 2: + IC(1.335 ns) + CELL(0.711 ns) = 3.515 ns; Loc. = LC_X34_Y5_N5; Fanout = 5; REG Node = 'inst5'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "2.046 ns" { key1 inst5 } "NODE_NAME" } "" } } { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/Block1.bdf" { { 392 88 152 472 "inst5" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 62.02 % " "Info: Total cell delay = 2.180 ns ( 62.02 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.335 ns 37.98 % " "Info: Total interconnect delay = 1.335 ns ( 37.98 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "3.515 ns" { key1 inst5 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.515 ns" { key1 key1~out0 inst5 } { 0.000ns 0.000ns 1.335ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "key1 source 3.515 ns - Longest register " "Info: - Longest clock path from clock \"key1\" to source register is 3.515 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns key1 1 CLK PIN_121 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_121; Fanout = 1; CLK Node = 'key1'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "" { key1 } "NODE_NAME" } "" } } { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/Block1.bdf" { { 424 -88 80 440 "key1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.335 ns) + CELL(0.711 ns) 3.515 ns inst5 2 REG LC_X34_Y5_N5 5 " "Info: 2: + IC(1.335 ns) + CELL(0.711 ns) = 3.515 ns; Loc. = LC_X34_Y5_N5; Fanout = 5; REG Node = 'inst5'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "2.046 ns" { key1 inst5 } "NODE_NAME" } "" } } { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/Block1.bdf" { { 392 88 152 472 "inst5" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 62.02 % " "Info: Total cell delay = 2.180 ns ( 62.02 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.335 ns 37.98 % " "Info: Total interconnect delay = 1.335 ns ( 37.98 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "3.515 ns" { key1 inst5 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.515 ns" { key1 key1~out0 inst5 } { 0.000ns 0.000ns 1.335ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "3.515 ns" { key1 inst5 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.515 ns" { key1 key1~out0 inst5 } { 0.000ns 0.000ns 1.335ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "3.515 ns" { key1 inst5 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.515 ns" { key1 key1~out0 inst5 } { 0.000ns 0.000ns 1.335ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/Block1.bdf" { { 392 88 152 472 "inst5" "" } } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/Block1.bdf" { { 392 88 152 472 "inst5" "" } } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "0.837 ns" { inst5 inst5 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.837 ns" { inst5 inst5 } { 0.000ns 0.528ns } { 0.000ns 0.309ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "3.515 ns" { key1 inst5 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.515 ns" { key1 key1~out0 inst5 } { 0.000ns 0.000ns 1.335ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "3.515 ns" { key1 inst5 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.515 ns" { key1 key1~out0 inst5 } { 0.000ns 0.000ns 1.335ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "" { inst5 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { inst5 } {  } {  } } } { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/Block1.bdf" { { 392 88 152 472 "inst5" "" } } } }  } 0}