📄 cnt_4b.tan.qmsg

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💻 QMSG
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "key1 " "Info: Assuming node \"key1\" is an undefined clock" {  } { { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/Block1.bdf" { { 424 -88 80 440 "key1" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "key1" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "int_div:inst14\|ClockOut register cnt_4b:inst\|cnt\[0\] register cnt_4b:inst\|cnt\[3\] 17.618 ns " "Info: Slack time is 17.618 ns for clock \"int_div:inst14\|ClockOut\" between source register \"cnt_4b:inst\|cnt\[0\]\" and destination register \"cnt_4b:inst\|cnt\[3\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT_RESTRICTED" "275.03 MHz " "Info: Fmax is restricted to 275.03 MHz due to tcl and tch limits" {  } {  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "19.739 ns + Largest register register " "Info: + Largest register to register requirement is 19.739 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.000 ns + " "Info: + Setup relationship between source and destination is 20.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 20.000 ns " "Info: + Latch edge is 20.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination int_div:inst14\|ClockOut 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"int_div:inst14\|ClockOut\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source int_div:inst14\|ClockOut 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"int_div:inst14\|ClockOut\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "int_div:inst14\|ClockOut destination 4.160 ns + Shortest register " "Info: + Shortest clock path from clock \"int_div:inst14\|ClockOut\" to destination register is 4.160 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst14\|ClockOut 1 CLK LC_X8_Y10_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y10_N5; Fanout = 4; CLK Node = 'int_div:inst14\|ClockOut'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "" { int_div:inst14|ClockOut } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/int_div.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.449 ns) + CELL(0.711 ns) 4.160 ns cnt_4b:inst\|cnt\[3\] 2 REG LC_X34_Y5_N9 9 " "Info: 2: + IC(3.449 ns) + CELL(0.711 ns) = 4.160 ns; Loc. = LC_X34_Y5_N9; Fanout = 9; REG Node = 'cnt_4b:inst\|cnt\[3\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[3] } "NODE_NAME" } "" } } { "cnt_4b.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/cnt_4b.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 17.09 % " "Info: Total cell delay = 0.711 ns ( 17.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.449 ns 82.91 % " "Info: Total interconnect delay = 3.449 ns ( 82.91 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[3] } { 0.000ns 3.449ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "int_div:inst14\|ClockOut source 4.160 ns - Longest register " "Info: - Longest clock path from clock \"int_div:inst14\|ClockOut\" to source register is 4.160 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst14\|ClockOut 1 CLK LC_X8_Y10_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y10_N5; Fanout = 4; CLK Node = 'int_div:inst14\|ClockOut'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "" { int_div:inst14|ClockOut } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/int_div.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.449 ns) + CELL(0.711 ns) 4.160 ns cnt_4b:inst\|cnt\[0\] 2 REG LC_X34_Y5_N6 11 " "Info: 2: + IC(3.449 ns) + CELL(0.711 ns) = 4.160 ns; Loc. = LC_X34_Y5_N6; Fanout = 11; REG Node = 'cnt_4b:inst\|cnt\[0\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[0] } "NODE_NAME" } "" } } { "cnt_4b.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/cnt_4b.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 17.09 % " "Info: Total cell delay = 0.711 ns ( 17.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.449 ns 82.91 % " "Info: Total interconnect delay = 3.449 ns ( 82.91 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[0] } { 0.000ns 3.449ns } { 0.000ns 0.711ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[3] } { 0.000ns 3.449ns } { 0.000ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[0] } { 0.000ns 3.449ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "cnt_4b.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/cnt_4b.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "cnt_4b.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/cnt_4b.vhd" 35 -1 0 } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[3] } { 0.000ns 3.449ns } { 0.000ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[0] } { 0.000ns 3.449ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.121 ns - Longest register register " "Info: - Longest register to register delay is 2.121 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt_4b:inst\|cnt\[0\] 1 REG LC_X34_Y5_N6 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y5_N6; Fanout = 11; REG Node = 'cnt_4b:inst\|cnt\[0\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "" { cnt_4b:inst|cnt[0] } "NODE_NAME" } "" } } { "cnt_4b.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/cnt_4b.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.599 ns) + CELL(0.575 ns) 1.174 ns cnt_4b:inst\|cnt\[0\]~46COUT1_62 2 COMB LC_X34_Y5_N6 2 " "Info: 2: + IC(0.599 ns) + CELL(0.575 ns) = 1.174 ns; Loc. = LC_X34_Y5_N6; Fanout = 2; COMB Node = 'cnt_4b:inst\|cnt\[0\]~46COUT1_62'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "1.174 ns" { cnt_4b:inst|cnt[0] cnt_4b:inst|cnt[0]~46COUT1_62 } "NODE_NAME" } "" } } { "cnt_4b.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/cnt_4b.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.254 ns cnt_4b:inst\|cnt\[1\]~50COUT1 3 COMB LC_X34_Y5_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.254 ns; Loc. = LC_X34_Y5_N7; Fanout = 2; COMB Node = 'cnt_4b:inst\|cnt\[1\]~50COUT1'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "0.080 ns" { cnt_4b:inst|cnt[0]~46COUT1_62 cnt_4b:inst|cnt[1]~50COUT1 } "NODE_NAME" } "" } } { "cnt_4b.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/cnt_4b.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.334 ns cnt_4b:inst\|cnt\[2\]~54COUT1_63 4 COMB LC_X34_Y5_N8 1 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.334 ns; Loc. = LC_X34_Y5_N8; Fanout = 1; COMB Node = 'cnt_4b:inst\|cnt\[2\]~54COUT1_63'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "0.080 ns" { cnt_4b:inst|cnt[1]~50COUT1 cnt_4b:inst|cnt[2]~54COUT1_63 } "NODE_NAME" } "" } } { "cnt_4b.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/cnt_4b.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.787 ns) 2.121 ns cnt_4b:inst\|cnt\[3\] 5 REG LC_X34_Y5_N9 9 " "Info: 5: + IC(0.000 ns) + CELL(0.787 ns) = 2.121 ns; Loc. = LC_X34_Y5_N9; Fanout = 9; REG Node = 'cnt_4b:inst\|cnt\[3\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "0.787 ns" { cnt_4b:inst|cnt[2]~54COUT1_63 cnt_4b:inst|cnt[3] } "NODE_NAME" } "" } } { "cnt_4b.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/cnt_4b.vhd" 35 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.522 ns 71.76 % " "Info: Total cell delay = 1.522 ns ( 71.76 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.599 ns 28.24 % " "Info: Total interconnect delay = 0.599 ns ( 28.24 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "2.121 ns" { cnt_4b:inst|cnt[0] cnt_4b:inst|cnt[0]~46COUT1_62 cnt_4b:inst|cnt[1]~50COUT1 cnt_4b:inst|cnt[2]~54COUT1_63 cnt_4b:inst|cnt[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.121 ns" { cnt_4b:inst|cnt[0] cnt_4b:inst|cnt[0]~46COUT1_62 cnt_4b:inst|cnt[1]~50COUT1 cnt_4b:inst|cnt[2]~54COUT1_63 cnt_4b:inst|cnt[3] } { 0.000ns 0.599ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.787ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[3] } { 0.000ns 3.449ns } { 0.000ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.160 ns" { int_div:inst14|ClockOut cnt_4b:inst|cnt[0] } { 0.000ns 3.449ns } { 0.000ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b_cmp.qrpt" Compiler "cnt_4b" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/db/cnt_4b.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/" "" "2.121 ns" { cnt_4b:inst|cnt[0] cnt_4b:inst|cnt[0]~46COUT1_62 cnt_4b:inst|cnt[1]~50COUT1 cnt_4b:inst|cnt[2]~54COUT1_63 cnt_4b:inst|cnt[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.121 ns" { cnt_4b:inst|cnt[0] cnt_4b:inst|cnt[0]~46COUT1_62 cnt_4b:inst|cnt[1]~50COUT1 cnt_4b:inst|cnt[2]~54COUT1_63 cnt_4b:inst|cnt[3] } { 0.000ns 0.599ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.787ns } } }  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "int_div:inst14\|Temp2 " "Info: No valid register-to-register data paths exist for clock \"int_div:inst14\|Temp2\"" {  } {  } 0}
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