cnt_4b.map.qmsg

很多vhdl例程代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1.04 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1.04 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Sep 15 17:40:12 2006 " "Info: Processing started: Fri Sep 15 17:40:12 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off cnt_4b -c cnt_4b " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cnt_4b -c cnt_4b" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cnt_4b.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cnt_4b.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cnt_4b-one " "Info: Found design unit 1: cnt_4b-one" {  } { { "cnt_4b.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/cnt_4b.vhd" 34 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 cnt_4b " "Info: Found entity 1: cnt_4b" {  } { { "cnt_4b.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/cnt_4b.vhd" 26 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decl7s.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file decl7s.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 decl7s-ONE " "Info: Found design unit 1: decl7s-ONE" {  } { { "decl7s.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/decl7s.vhd" 35 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 decl7s " "Info: Found entity 1: decl7s" {  } { { "decl7s.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/decl7s.vhd" 28 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "int_div.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file int_div.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 int_div-Devider " "Info: Found design unit 1: int_div-Devider" {  } { { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/int_div.vhd" 36 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 int_div " "Info: Found entity 1: int_div" {  } { { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/int_div.vhd" 27 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Block1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Block1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Block1 " "Info: Found entity 1: Block1" {  } { { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/Block1.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Block1 " "Info: Elaborating entity \"Block1\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cnt_4b cnt_4b:inst " "Info: Elaborating entity \"cnt_4b\" for hierarchy \"cnt_4b:inst\"" {  } { { "Block1.bdf" "inst" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/Block1.bdf" { { 272 288 416 368 "inst" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "int_div int_div:inst14 " "Info: Elaborating entity \"int_div\" for hierarchy \"int_div:inst14\"" {  } { { "Block1.bdf" "inst14" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/Block1.bdf" { { 256 112 248 352 "inst14" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decl7s decl7s:inst1 " "Info: Elaborating entity \"decl7s\" for hierarchy \"decl7s:inst1\"" {  } { { "Block1.bdf" "inst1" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/Block1.bdf" { { 272 480 608 368 "inst1" "" } } } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "decl7s.vhd(58) " "Info: VHDL Case Statement information at decl7s.vhd(58): OTHERS choice is never selected" {  } { { "decl7s.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/decl7s.vhd" 58 0 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "dig\[7\] GND " "Warning: Pin \"dig\[7\]\" stuck at GND" {  } { { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/Block1.bdf" { { 160 552 728 176 "dig\[7..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "dig\[6\] GND " "Warning: Pin \"dig\[6\]\" stuck at GND" {  } { { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/Block1.bdf" { { 160 552 728 176 "dig\[7..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "dig\[5\] GND " "Warning: Pin \"dig\[5\]\" stuck at GND" {  } { { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/Block1.bdf" { { 160 552 728 176 "dig\[7..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "dig\[4\] GND " "Warning: Pin \"dig\[4\]\" stuck at GND" {  } { { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/Block1.bdf" { { 160 552 728 176 "dig\[7..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "dig\[3\] GND " "Warning: Pin \"dig\[3\]\" stuck at GND" {  } { { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/Block1.bdf" { { 160 552 728 176 "dig\[7..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "dig\[2\] GND " "Warning: Pin \"dig\[2\]\" stuck at GND" {  } { { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/Block1.bdf" { { 160 552 728 176 "dig\[7..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "dig\[1\] GND " "Warning: Pin \"dig\[1\]\" stuck at GND" {  } { { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/Block1.bdf" { { 160 552 728 176 "dig\[7..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "dig\[0\] GND " "Warning: Pin \"dig\[0\]\" stuck at GND" {  } { { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/Block1.bdf" { { 160 552 728 176 "dig\[7..0\]" "" } } } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "seg\[7\] VCC " "Warning: Pin \"seg\[7\]\" stuck at VCC" {  } { { "Block1.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/Block1.bdf" { { 296 648 824 312 "seg\[7..0\]" "" } } } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "106 " "Info: Implemented 106 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "19 " "Info: Implemented 19 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "84 " "Info: Implemented 84 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 10 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 15 17:40:15 2006 " "Info: Processing ended: Fri Sep 15 17:40:15 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}