cnt_4b.hier_info

很多vhdl例程代码

|Block1
led8 <= inst7.DB_MAX_OUTPUT_PORT_TYPE
clock_48M => int_div:inst14.Clockin
key2 => cnt_4b:inst.rst
key2 => led2.DATAIN
key1 => inst5.CLK
led1 <= inst9.DB_MAX_OUTPUT_PORT_TYPE
led2 <= key2.DB_MAX_OUTPUT_PORT_TYPE
dig[0] <= <GND>
dig[1] <= <GND>
dig[2] <= <GND>
dig[3] <= <GND>
dig[4] <= <GND>
dig[5] <= <GND>
dig[6] <= <GND>
dig[7] <= <GND>
seg[0] <= decl7s:inst1.seg[0]
seg[1] <= decl7s:inst1.seg[1]
seg[2] <= decl7s:inst1.seg[2]
seg[3] <= decl7s:inst1.seg[3]
seg[4] <= decl7s:inst1.seg[4]
seg[5] <= decl7s:inst1.seg[5]
seg[6] <= decl7s:inst1.seg[6]
seg[7] <= decl7s:inst1.seg[7]


|Block1|cnt_4b:inst
clock => cnt[2].CLK
clock => cnt[1].CLK
clock => cnt[0].CLK
clock => cnt[3].CLK
rst => cnt~4.OUTPUTSELECT
rst => cnt~5.OUTPUTSELECT
rst => cnt~6.OUTPUTSELECT
rst => cnt~7.OUTPUTSELECT
ena => cnt~0.OUTPUTSELECT
ena => cnt~1.OUTPUTSELECT
ena => cnt~2.OUTPUTSELECT
ena => cnt~3.OUTPUTSELECT
dout[0] <= cnt[0].DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= cnt[1].DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= cnt[2].DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= cnt[3].DB_MAX_OUTPUT_PORT_TYPE
cout <= cout~2.DB_MAX_OUTPUT_PORT_TYPE


|Block1|int_div:inst14
Clockin => Counter[24].CLK
Clockin => Counter[23].CLK
Clockin => Counter[22].CLK
Clockin => Counter[21].CLK
Clockin => Counter[20].CLK
Clockin => Counter[19].CLK
Clockin => Counter[18].CLK
Clockin => Counter[17].CLK
Clockin => Counter[16].CLK
Clockin => Counter[15].CLK
Clockin => Counter[14].CLK
Clockin => Counter[13].CLK
Clockin => Counter[12].CLK
Clockin => Counter[11].CLK
Clockin => Counter[10].CLK
Clockin => Counter[9].CLK
Clockin => Counter[8].CLK
Clockin => Counter[7].CLK
Clockin => Counter[6].CLK
Clockin => Counter[5].CLK
Clockin => Counter[4].CLK
Clockin => Counter[3].CLK
Clockin => Counter[2].CLK
Clockin => Counter[1].CLK
Clockin => Counter[0].CLK
Clockin => Temp1.CLK
Clockin => Counter[25].CLK
Clockin => Temp2.CLK
ClockOut <= ClockOut~0.DB_MAX_OUTPUT_PORT_TYPE


|Block1|decl7s:inst1
d[0] => Mux~0.IN19
d[0] => Mux~1.IN19
d[0] => Mux~2.IN19
d[0] => Mux~3.IN19
d[0] => Mux~4.IN19
d[0] => Mux~5.IN19
d[0] => Mux~6.IN19
d[1] => Mux~0.IN18
d[1] => Mux~1.IN18
d[1] => Mux~2.IN18
d[1] => Mux~3.IN18
d[1] => Mux~4.IN18
d[1] => Mux~5.IN18
d[1] => Mux~6.IN18
d[2] => Mux~0.IN17
d[2] => Mux~1.IN17
d[2] => Mux~2.IN17
d[2] => Mux~3.IN17
d[2] => Mux~4.IN17
d[2] => Mux~5.IN17
d[2] => Mux~6.IN17
d[3] => Mux~0.IN16
d[3] => Mux~1.IN16
d[3] => Mux~2.IN16
d[3] => Mux~3.IN16
d[3] => Mux~4.IN16
d[3] => Mux~5.IN16
d[3] => Mux~6.IN16
seg[0] <= Mux~6.DB_MAX_OUTPUT_PORT_TYPE
seg[1] <= Mux~5.DB_MAX_OUTPUT_PORT_TYPE
seg[2] <= Mux~4.DB_MAX_OUTPUT_PORT_TYPE
seg[3] <= Mux~3.DB_MAX_OUTPUT_PORT_TYPE
seg[4] <= Mux~2.DB_MAX_OUTPUT_PORT_TYPE
seg[5] <= Mux~1.DB_MAX_OUTPUT_PORT_TYPE
seg[6] <= Mux~0.DB_MAX_OUTPUT_PORT_TYPE
seg[7] <= <VCC>