cnt_4b.map.rpt

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; decl7s.vhd                       ; yes             ; User VHDL File                     ; E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/decl7s.vhd  ;
; int_div.vhd                      ; yes             ; User VHDL File                     ; E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/int_div.vhd ;
; Block1.bdf                       ; yes             ; User Block Diagram/Schematic File  ; E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/Block1.bdf  ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------------+


+-----------------------------------------------+
; Analysis & Synthesis Resource Usage Summary   ;
+-----------------------------------+-----------+
; Resource                          ; Usage     ;
+-----------------------------------+-----------+
; Total logic elements              ; 84        ;
; Total combinational functions     ; 65        ;
;     -- Total 4-input functions    ; 22        ;
;     -- Total 3-input functions    ; 0         ;
;     -- Total 2-input functions    ; 14        ;
;     -- Total 1-input functions    ; 29        ;
;     -- Total 0-input functions    ; 0         ;
; Combinational cells for routing   ; 0         ;
; Total registers                   ; 33        ;
; Total logic cells in carry chains ; 30        ;
; I/O pins                          ; 22        ;
; Maximum fan-out node              ; clock_48M ;
; Maximum fan-out                   ; 28        ;
; Total fan-out                     ; 241       ;
; Average fan-out                   ; 2.27      ;
+-----------------------------------+-----------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                          ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name    ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------+
; |Block1                    ; 84 (1)      ; 33           ; 0           ; 22   ; 0            ; 51 (0)       ; 19 (1)            ; 14 (0)           ; 30 (0)          ; |Block1                ;
;    |cnt_4b:inst|           ; 5 (5)       ; 4            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |Block1|cnt_4b:inst    ;
;    |decl7s:inst1|          ; 7 (7)       ; 0            ; 0           ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |Block1|decl7s:inst1   ;
;    |int_div:inst14|        ; 71 (71)     ; 28           ; 0           ; 0    ; 0            ; 43 (43)      ; 18 (18)           ; 10 (10)          ; 26 (26)         ; |Block1|int_div:inst14 ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 33    ;
; Number of registers using Synchronous Clear  ; 4     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 2     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------+
; Parameter Settings for User Entity Instance: int_div:inst14 ;
+----------------+----------+---------------------------------+
; Parameter Name ; Value    ; Type                            ;
+----------------+----------+---------------------------------+
; n              ; 48000000 ; Untyped                         ;
+----------------+----------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_8_cnt_4b/cnt_4b.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1.04 SJ Full Version
    Info: Processing started: Fri Sep 15 17:40:12 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cnt_4b -c cnt_4b
Info: Found 2 design units, including 1 entities, in source file cnt_4b.vhd
    Info: Found design unit 1: cnt_4b-one
    Info: Found entity 1: cnt_4b
Info: Found 2 design units, including 1 entities, in source file decl7s.vhd
    Info: Found design unit 1: decl7s-ONE
    Info: Found entity 1: decl7s
Info: Found 2 design units, including 1 entities, in source file int_div.vhd
    Info: Found design unit 1: int_div-Devider
    Info: Found entity 1: int_div
Info: Found 1 design units, including 1 entities, in source file Block1.bdf
    Info: Found entity 1: Block1
Info: Elaborating entity "Block1" for the top level hierarchy
Info: Elaborating entity "cnt_4b" for hierarchy "cnt_4b:inst"
Info: Elaborating entity "int_div" for hierarchy "int_div:inst14"
Info: Elaborating entity "decl7s" for hierarchy "decl7s:inst1"
Info: VHDL Case Statement information at decl7s.vhd(58): OTHERS choice is never selected
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "dig[7]" stuck at GND
    Warning: Pin "dig[6]" stuck at GND
    Warning: Pin "dig[5]" stuck at GND
    Warning: Pin "dig[4]" stuck at GND
    Warning: Pin "dig[3]" stuck at GND
    Warning: Pin "dig[2]" stuck at GND
    Warning: Pin "dig[1]" stuck at GND
    Warning: Pin "dig[0]" stuck at GND
    Warning: Pin "seg[7]" stuck at VCC
Info: Implemented 106 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 19 output pins
    Info: Implemented 84 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings
    Info: Processing ended: Fri Sep 15 17:40:15 2006
    Info: Elapsed time: 00:00:03