keyled.tan.qmsg

很多vhdl例程代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1.04 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1.04 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Sep 15 14:17:55 2006 " "Info: Processing started: Fri Sep 15 14:17:55 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off keyled -c keyled --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off keyled -c keyled --timing_analysis_only" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "key\[7\] led\[6\] 16.532 ns Longest " "Info: Longest tpd from source pin \"key\[7\]\" to destination pin \"led\[6\]\" is 16.532 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns key\[7\] 1 PIN PIN_156 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_156; Fanout = 4; PIN Node = 'key\[7\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_3_keyled/db/keyled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_3_keyled/db/keyled_cmp.qrpt" Compiler "keyled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_3_keyled/db/keyled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_3_keyled/" "" "" { key[7] } "NODE_NAME" } "" } } { "keyled.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_3_keyled/keyled.vhd" 28 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.990 ns) + CELL(0.292 ns) 7.751 ns reduce_nor~91 2 COMB LC_X34_Y4_N5 3 " "Info: 2: + IC(5.990 ns) + CELL(0.292 ns) = 7.751 ns; Loc. = LC_X34_Y4_N5; Fanout = 3; COMB Node = 'reduce_nor~91'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_3_keyled/db/keyled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_3_keyled/db/keyled_cmp.qrpt" Compiler "keyled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_3_keyled/db/keyled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_3_keyled/" "" "6.282 ns" { key[7] reduce_nor~91 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 8.047 ns reduce_nor~94 3 COMB LC_X34_Y4_N6 3 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 8.047 ns; Loc. = LC_X34_Y4_N6; Fanout = 3; COMB Node = 'reduce_nor~94'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_3_keyled/db/keyled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_3_keyled/db/keyled_cmp.qrpt" Compiler "keyled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_3_keyled/db/keyled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_3_keyled/" "" "0.296 ns" { reduce_nor~91 reduce_nor~94 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.226 ns) + CELL(0.590 ns) 9.863 ns reduce_nor~6 4 COMB LC_X34_Y5_N4 1 " "Info: 4: + IC(1.226 ns) + CELL(0.590 ns) = 9.863 ns; Loc. = LC_X34_Y5_N4; Fanout = 1; COMB Node = 'reduce_nor~6'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_3_keyled/db/keyled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_3_keyled/db/keyled_cmp.qrpt" Compiler "keyled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_3_keyled/db/keyled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_3_keyled/" "" "1.816 ns" { reduce_nor~94 reduce_nor~6 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.545 ns) + CELL(2.124 ns) 16.532 ns led\[6\] 5 PIN PIN_48 0 " "Info: 5: + IC(4.545 ns) + CELL(2.124 ns) = 16.532 ns; Loc. = PIN_48; Fanout = 0; PIN Node = 'led\[6\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_3_keyled/db/keyled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_3_keyled/db/keyled_cmp.qrpt" Compiler "keyled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_3_keyled/db/keyled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_3_keyled/" "" "6.669 ns" { reduce_nor~6 led[6] } "NODE_NAME" } "" } } { "keyled.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_3_keyled/keyled.vhd" 29 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.589 ns 27.76 % " "Info: Total cell delay = 4.589 ns ( 27.76 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.943 ns 72.24 % " "Info: Total interconnect delay = 11.943 ns ( 72.24 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_3_keyled/db/keyled_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_3_keyled/db/keyled_cmp.qrpt" Compiler "keyled" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_3_keyled/db/keyled.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickEDA/ep1c6_3_keyled/" "" "16.532 ns" { key[7] reduce_nor~91 reduce_nor~94 reduce_nor~6 led[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "16.532 ns" { key[7] key[7]~out0 reduce_nor~91 reduce_nor~94 reduce_nor~6 led[6] } { 0.000ns 0.000ns 5.990ns 0.182ns 1.226ns 4.545ns } { 0.000ns 1.469ns 0.292ns 0.114ns 0.590ns 2.124ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 15 14:17:55 2006 " "Info: Processing ended: Fri Sep 15 14:17:55 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}