led_water.tan.qmsg

很多vhdl例程代码

{ "Info" "ITDB_FULL_SLACK_RESULT" "clock register int_div:inst\|Counter\[12\] register int_div:inst\|Counter\[23\] 13.404 ns " "Info: Slack time is 13.404 ns for clock \"clock\" between source register \"int_div:inst\|Counter\[12\]\" and destination register \"int_div:inst\|Counter\[23\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "151.61 MHz 6.596 ns " "Info: Fmax is 151.61 MHz (period= 6.596 ns)" {  } {  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "19.739 ns + Largest register register " "Info: + Largest register to register requirement is 19.739 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.000 ns + " "Info: + Setup relationship between source and destination is 20.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 20.000 ns " "Info: + Latch edge is 20.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clock 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clock\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clock 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clock\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.903 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_28 28 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 28; CLK Node = 'clock'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "" { clock } "NODE_NAME" } "" } } { "led_water.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/led_water.bdf" { { 80 -48 120 96 "clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns int_div:inst\|Counter\[23\] 2 REG LC_X11_Y6_N9 5 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X11_Y6_N9; Fanout = 5; REG Node = 'int_div:inst\|Counter\[23\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "1.434 ns" { clock int_div:inst|Counter[23] } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.09 % " "Info: Total cell delay = 2.180 ns ( 75.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns 24.91 % " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "2.903 ns" { clock int_div:inst|Counter[23] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clock clock~out0 int_div:inst|Counter[23] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.903 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 2.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clock 1 CLK PIN_28 28 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 28; CLK Node = 'clock'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "" { clock } "NODE_NAME" } "" } } { "led_water.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/led_water.bdf" { { 80 -48 120 96 "clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.711 ns) 2.903 ns int_div:inst\|Counter\[12\] 2 REG LC_X10_Y8_N2 4 " "Info: 2: + IC(0.723 ns) + CELL(0.711 ns) = 2.903 ns; Loc. = LC_X10_Y8_N2; Fanout = 4; REG Node = 'int_div:inst\|Counter\[12\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "1.434 ns" { clock int_div:inst|Counter[12] } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.09 % " "Info: Total cell delay = 2.180 ns ( 75.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns 24.91 % " "Info: Total interconnect delay = 0.723 ns ( 24.91 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "2.903 ns" { clock int_div:inst|Counter[12] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clock clock~out0 int_div:inst|Counter[12] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "2.903 ns" { clock int_div:inst|Counter[23] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clock clock~out0 int_div:inst|Counter[23] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "2.903 ns" { clock int_div:inst|Counter[12] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clock clock~out0 int_div:inst|Counter[12] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/int_div.vhd" 37 -1 0 } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "2.903 ns" { clock int_div:inst|Counter[23] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clock clock~out0 int_div:inst|Counter[23] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "2.903 ns" { clock int_div:inst|Counter[12] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clock clock~out0 int_div:inst|Counter[12] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.335 ns - Longest register register " "Info: - Longest register to register delay is 6.335 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst\|Counter\[12\] 1 REG LC_X10_Y8_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y8_N2; Fanout = 4; REG Node = 'int_div:inst\|Counter\[12\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "" { int_div:inst|Counter[12] } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.375 ns) + CELL(0.590 ns) 2.965 ns int_div:inst\|reduce_nor~319 2 COMB LC_X10_Y8_N0 1 " "Info: 2: + IC(2.375 ns) + CELL(0.590 ns) = 2.965 ns; Loc. = LC_X10_Y8_N0; Fanout = 1; COMB Node = 'int_div:inst\|reduce_nor~319'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "2.965 ns" { int_div:inst|Counter[12] int_div:inst|reduce_nor~319 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.183 ns) + CELL(0.442 ns) 4.590 ns int_div:inst\|reduce_nor~0 3 COMB LC_X10_Y7_N7 11 " "Info: 3: + IC(1.183 ns) + CELL(0.442 ns) = 4.590 ns; Loc. = LC_X10_Y7_N7; Fanout = 11; COMB Node = 'int_div:inst\|reduce_nor~0'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "1.625 ns" { int_div:inst|reduce_nor~319 int_div:inst|reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.478 ns) 6.335 ns int_div:inst\|Counter\[23\] 4 REG LC_X11_Y6_N9 5 " "Info: 4: + IC(1.267 ns) + CELL(0.478 ns) = 6.335 ns; Loc. = LC_X11_Y6_N9; Fanout = 5; REG Node = 'int_div:inst\|Counter\[23\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "1.745 ns" { int_div:inst|reduce_nor~0 int_div:inst|Counter[23] } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.510 ns 23.84 % " "Info: Total cell delay = 1.510 ns ( 23.84 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.825 ns 76.16 % " "Info: Total interconnect delay = 4.825 ns ( 76.16 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "6.335 ns" { int_div:inst|Counter[12] int_div:inst|reduce_nor~319 int_div:inst|reduce_nor~0 int_div:inst|Counter[23] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.335 ns" { int_div:inst|Counter[12] int_div:inst|reduce_nor~319 int_div:inst|reduce_nor~0 int_div:inst|Counter[23] } { 0.000ns 2.375ns 1.183ns 1.267ns } { 0.000ns 0.590ns 0.442ns 0.478ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "2.903 ns" { clock int_div:inst|Counter[23] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clock clock~out0 int_div:inst|Counter[23] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "2.903 ns" { clock int_div:inst|Counter[12] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.903 ns" { clock clock~out0 int_div:inst|Counter[12] } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "6.335 ns" { int_div:inst|Counter[12] int_div:inst|reduce_nor~319 int_div:inst|reduce_nor~0 int_div:inst|Counter[23] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.335 ns" { int_div:inst|Counter[12] int_div:inst|reduce_nor~319 int_div:inst|reduce_nor~0 int_div:inst|Counter[23] } { 0.000ns 2.375ns 1.183ns 1.267ns } { 0.000ns 0.590ns 0.442ns 0.478ns } } }  } 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "int_div:inst\|ClockOut register ledwater:inst1\|led_r\[3\] register ledwater:inst1\|led_r\[4\] 1.097 ns " "Info: Minimum slack time is 1.097 ns for clock \"int_div:inst\|ClockOut\" between source register \"ledwater:inst1\|led_r\[3\]\" and destination register \"ledwater:inst1\|led_r\[4\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.888 ns + Shortest register register " "Info: + Shortest register to register delay is 0.888 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ledwater:inst1\|led_r\[3\] 1 REG LC_X1_Y5_N1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y5_N1; Fanout = 3; REG Node = 'ledwater:inst1\|led_r\[3\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "" { ledwater:inst1|led_r[3] } "NODE_NAME" } "" } } { "ledwater.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/ledwater.vhd" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.579 ns) + CELL(0.309 ns) 0.888 ns ledwater:inst1\|led_r\[4\] 2 REG LC_X1_Y5_N8 3 " "Info: 2: + IC(0.579 ns) + CELL(0.309 ns) = 0.888 ns; Loc. = LC_X1_Y5_N8; Fanout = 3; REG Node = 'ledwater:inst1\|led_r\[4\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "0.888 ns" { ledwater:inst1|led_r[3] ledwater:inst1|led_r[4] } "NODE_NAME" } "" } } { "ledwater.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/ledwater.vhd" 36 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns 34.80 % " "Info: Total cell delay = 0.309 ns ( 34.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.579 ns 65.20 % " "Info: Total interconnect delay = 0.579 ns ( 65.20 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "0.888 ns" { ledwater:inst1|led_r[3] ledwater:inst1|led_r[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.888 ns" { ledwater:inst1|led_r[3] ledwater:inst1|led_r[4] } { 0.0ns 0.579ns } { 0.0ns 0.309ns } } }  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination int_div:inst\|ClockOut 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"int_div:inst\|ClockOut\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source int_div:inst\|ClockOut 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"int_div:inst\|ClockOut\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "int_div:inst\|ClockOut destination 4.665 ns + Longest register " "Info: + Longest clock path from clock \"int_div:inst\|ClockOut\" to destination register is 4.665 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst\|ClockOut 1 CLK LC_X8_Y7_N2 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y7_N2; Fanout = 9; CLK Node = 'int_div:inst\|ClockOut'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "" { int_div:inst|ClockOut } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/int_div.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.954 ns) + CELL(0.711 ns) 4.665 ns ledwater:inst1\|led_r\[4\] 2 REG LC_X1_Y5_N8 3 " "Info: 2: + IC(3.954 ns) + CELL(0.711 ns) = 4.665 ns; Loc. = LC_X1_Y5_N8; Fanout = 3; REG Node = 'ledwater:inst1\|led_r\[4\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[4] } "NODE_NAME" } "" } } { "ledwater.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/ledwater.vhd" 36 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 15.24 % " "Info: Total cell delay = 0.711 ns ( 15.24 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.954 ns 84.76 % " "Info: Total interconnect delay = 3.954 ns ( 84.76 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[4] } { 0.0ns 3.954ns } { 0.0ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "int_div:inst\|ClockOut source 4.665 ns - Shortest register " "Info: - Shortest clock path from clock \"int_div:inst\|ClockOut\" to source register is 4.665 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst\|ClockOut 1 CLK LC_X8_Y7_N2 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y7_N2; Fanout = 9; CLK Node = 'int_div:inst\|ClockOut'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "" { int_div:inst|ClockOut } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/int_div.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.954 ns) + CELL(0.711 ns) 4.665 ns ledwater:inst1\|led_r\[3\] 2 REG LC_X1_Y5_N1 3 " "Info: 2: + IC(3.954 ns) + CELL(0.711 ns) = 4.665 ns; Loc. = LC_X1_Y5_N1; Fanout = 3; REG Node = 'ledwater:inst1\|led_r\[3\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[3] } "NODE_NAME" } "" } } { "ledwater.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/ledwater.vhd" 36 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 15.24 % " "Info: Total cell delay = 0.711 ns ( 15.24 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.954 ns 84.76 % " "Info: Total interconnect delay = 3.954 ns ( 84.76 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[3] } { 0.0ns 3.954ns } { 0.0ns 0.711ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[4] } { 0.0ns 3.954ns } { 0.0ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[3] } { 0.0ns 3.954ns } { 0.0ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "ledwater.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/ledwater.vhd" 36 -1 0 } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "ledwater.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/ledwater.vhd" 36 -1 0 } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[4] } { 0.0ns 3.954ns } { 0.0ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[3] } { 0.0ns 3.954ns } { 0.0ns 0.711ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "0.888 ns" { ledwater:inst1|led_r[3] ledwater:inst1|led_r[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.888 ns" { ledwater:inst1|led_r[3] ledwater:inst1|led_r[4] } { 0.0ns 0.579ns } { 0.0ns 0.309ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[4] } { 0.0ns 3.954ns } { 0.0ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[3] } { 0.0ns 3.954ns } { 0.0ns 0.711ns } } }  } 0}