led_water.tan.qmsg

很多vhdl例程代码

{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off led_water -c led_water --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off led_water -c led_water --timing_analysis_only" {  } {  } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "int_div:inst\|ClockOut register ledwater:inst1\|led_r\[6\] register ledwater:inst1\|led_r\[3\] 17.313 ns " "Info: Slack time is 17.313 ns for clock \"int_div:inst\|ClockOut\" between source register \"ledwater:inst1\|led_r\[6\]\" and destination register \"ledwater:inst1\|led_r\[3\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT_RESTRICTED" "275.03 MHz " "Info: Fmax is restricted to 275.03 MHz due to tcl and tch limits" {  } {  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "19.739 ns + Largest register register " "Info: + Largest register to register requirement is 19.739 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.000 ns + " "Info: + Setup relationship between source and destination is 20.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 20.000 ns " "Info: + Latch edge is 20.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination int_div:inst\|ClockOut 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"int_div:inst\|ClockOut\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source int_div:inst\|ClockOut 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"int_div:inst\|ClockOut\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "int_div:inst\|ClockOut destination 4.665 ns + Shortest register " "Info: + Shortest clock path from clock \"int_div:inst\|ClockOut\" to destination register is 4.665 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst\|ClockOut 1 CLK LC_X8_Y7_N2 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y7_N2; Fanout = 9; CLK Node = 'int_div:inst\|ClockOut'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "" { int_div:inst|ClockOut } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/int_div.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.954 ns) + CELL(0.711 ns) 4.665 ns ledwater:inst1\|led_r\[3\] 2 REG LC_X1_Y5_N1 3 " "Info: 2: + IC(3.954 ns) + CELL(0.711 ns) = 4.665 ns; Loc. = LC_X1_Y5_N1; Fanout = 3; REG Node = 'ledwater:inst1\|led_r\[3\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[3] } "NODE_NAME" } "" } } { "ledwater.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/ledwater.vhd" 36 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 15.24 % " "Info: Total cell delay = 0.711 ns ( 15.24 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.954 ns 84.76 % " "Info: Total interconnect delay = 3.954 ns ( 84.76 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[3] } { 0.000ns 3.954ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "int_div:inst\|ClockOut source 4.665 ns - Longest register " "Info: - Longest clock path from clock \"int_div:inst\|ClockOut\" to source register is 4.665 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst\|ClockOut 1 CLK LC_X8_Y7_N2 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y7_N2; Fanout = 9; CLK Node = 'int_div:inst\|ClockOut'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "" { int_div:inst|ClockOut } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/int_div.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.954 ns) + CELL(0.711 ns) 4.665 ns ledwater:inst1\|led_r\[6\] 2 REG LC_X1_Y5_N9 3 " "Info: 2: + IC(3.954 ns) + CELL(0.711 ns) = 4.665 ns; Loc. = LC_X1_Y5_N9; Fanout = 3; REG Node = 'ledwater:inst1\|led_r\[6\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[6] } "NODE_NAME" } "" } } { "ledwater.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/ledwater.vhd" 36 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 15.24 % " "Info: Total cell delay = 0.711 ns ( 15.24 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.954 ns 84.76 % " "Info: Total interconnect delay = 3.954 ns ( 84.76 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[6] } { 0.000ns 3.954ns } { 0.000ns 0.711ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[3] } { 0.000ns 3.954ns } { 0.000ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[6] } { 0.000ns 3.954ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "ledwater.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/ledwater.vhd" 36 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "ledwater.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/ledwater.vhd" 36 -1 0 } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[3] } { 0.000ns 3.954ns } { 0.000ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[6] } { 0.000ns 3.954ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.426 ns - Longest register register " "Info: - Longest register to register delay is 2.426 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ledwater:inst1\|led_r\[6\] 1 REG LC_X1_Y5_N9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y5_N9; Fanout = 3; REG Node = 'ledwater:inst1\|led_r\[6\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "" { ledwater:inst1|led_r[6] } "NODE_NAME" } "" } } { "ledwater.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/ledwater.vhd" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.556 ns) + CELL(0.590 ns) 1.146 ns ledwater:inst1\|reduce_nor~110 2 COMB LC_X1_Y5_N6 9 " "Info: 2: + IC(0.556 ns) + CELL(0.590 ns) = 1.146 ns; Loc. = LC_X1_Y5_N6; Fanout = 9; COMB Node = 'ledwater:inst1\|reduce_nor~110'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "1.146 ns" { ledwater:inst1|led_r[6] ledwater:inst1|reduce_nor~110 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.542 ns) + CELL(0.738 ns) 2.426 ns ledwater:inst1\|led_r\[3\] 3 REG LC_X1_Y5_N1 3 " "Info: 3: + IC(0.542 ns) + CELL(0.738 ns) = 2.426 ns; Loc. = LC_X1_Y5_N1; Fanout = 3; REG Node = 'ledwater:inst1\|led_r\[3\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "1.280 ns" { ledwater:inst1|reduce_nor~110 ledwater:inst1|led_r[3] } "NODE_NAME" } "" } } { "ledwater.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/ledwater.vhd" 36 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.328 ns 54.74 % " "Info: Total cell delay = 1.328 ns ( 54.74 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.098 ns 45.26 % " "Info: Total interconnect delay = 1.098 ns ( 45.26 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "2.426 ns" { ledwater:inst1|led_r[6] ledwater:inst1|reduce_nor~110 ledwater:inst1|led_r[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.426 ns" { ledwater:inst1|led_r[6] ledwater:inst1|reduce_nor~110 ledwater:inst1|led_r[3] } { 0.000ns 0.556ns 0.542ns } { 0.000ns 0.590ns 0.738ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[3] } { 0.000ns 3.954ns } { 0.000ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.665 ns" { int_div:inst|ClockOut ledwater:inst1|led_r[6] } { 0.000ns 3.954ns } { 0.000ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water_cmp.qrpt" Compiler "led_water" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/db/led_water.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_2_led_water/" "" "2.426 ns" { ledwater:inst1|led_r[6] ledwater:inst1|reduce_nor~110 ledwater:inst1|led_r[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.426 ns" { ledwater:inst1|led_r[6] ledwater:inst1|reduce_nor~110 ledwater:inst1|led_r[3] } { 0.000ns 0.556ns 0.542ns } { 0.000ns 0.590ns 0.738ns } } }  } 0}