full_add.tan.rpt

很多vhdl例程代码

+-------+------------------------------------------------+-------+-------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------+
; tco                                                           ;
+-------+--------------+------------+-------+------+------------+
; Slack ; Required tco ; Actual tco ; From  ; To   ; From Clock ;
+-------+--------------+------------+-------+------+------------+
; N/A   ; None         ; 11.776 ns  ; inst2 ; cout ; key2       ;
; N/A   ; None         ; 11.775 ns  ; inst2 ; sum  ; key2       ;
; N/A   ; None         ; 11.265 ns  ; inst3 ; cout ; key1       ;
; N/A   ; None         ; 11.263 ns  ; inst3 ; sum  ; key1       ;
; N/A   ; None         ; 10.855 ns  ; inst1 ; sum  ; key3       ;
; N/A   ; None         ; 10.851 ns  ; inst1 ; cout ; key3       ;
; N/A   ; None         ; 10.419 ns  ; inst3 ; led1 ; key1       ;
; N/A   ; None         ; 9.954 ns   ; inst2 ; led2 ; key2       ;
; N/A   ; None         ; 9.934 ns   ; inst1 ; led3 ; key3       ;
+-------+--------------+------------+-------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1.04 SJ Full Version
    Info: Processing started: Fri Sep 15 16:56:13 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off full_add -c full_add --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "key1" is an undefined clock
    Info: Assuming node "key2" is an undefined clock
    Info: Assuming node "key3" is an undefined clock
Info: Clock "key1" Internal fmax is restricted to 275.03 MHz between source register "inst3" and destination register "inst3"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.041 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y2_N4; Fanout = 4; REG Node = 'inst3'
            Info: 2: + IC(0.563 ns) + CELL(0.478 ns) = 1.041 ns; Loc. = LC_X34_Y2_N4; Fanout = 4; REG Node = 'inst3'
            Info: Total cell delay = 0.478 ns ( 45.92 % )
            Info: Total interconnect delay = 0.563 ns ( 54.08 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "key1" to destination register is 3.511 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_121; Fanout = 1; CLK Node = 'key1'
                Info: 2: + IC(1.331 ns) + CELL(0.711 ns) = 3.511 ns; Loc. = LC_X34_Y2_N4; Fanout = 4; REG Node = 'inst3'
                Info: Total cell delay = 2.180 ns ( 62.09 % )
                Info: Total interconnect delay = 1.331 ns ( 37.91 % )
            Info: - Longest clock path from clock "key1" to source register is 3.511 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_121; Fanout = 1; CLK Node = 'key1'
                Info: 2: + IC(1.331 ns) + CELL(0.711 ns) = 3.511 ns; Loc. = LC_X34_Y2_N4; Fanout = 4; REG Node = 'inst3'
                Info: Total cell delay = 2.180 ns ( 62.09 % )
                Info: Total interconnect delay = 1.331 ns ( 37.91 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: Clock "key2" Internal fmax is restricted to 275.03 MHz between source register "inst2" and destination register "inst2"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.014 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y1_N2; Fanout = 4; REG Node = 'inst2'
            Info: 2: + IC(0.536 ns) + CELL(0.478 ns) = 1.014 ns; Loc. = LC_X34_Y1_N2; Fanout = 4; REG Node = 'inst2'
            Info: Total cell delay = 0.478 ns ( 47.14 % )
            Info: Total interconnect delay = 0.536 ns ( 52.86 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "key2" to destination register is 2.995 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_122; Fanout = 1; CLK Node = 'key2'
                Info: 2: + IC(0.815 ns) + CELL(0.711 ns) = 2.995 ns; Loc. = LC_X34_Y1_N2; Fanout = 4; REG Node = 'inst2'
                Info: Total cell delay = 2.180 ns ( 72.79 % )
                Info: Total interconnect delay = 0.815 ns ( 27.21 % )
            Info: - Longest clock path from clock "key2" to source register is 2.995 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_122; Fanout = 1; CLK Node = 'key2'
                Info: 2: + IC(0.815 ns) + CELL(0.711 ns) = 2.995 ns; Loc. = LC_X34_Y1_N2; Fanout = 4; REG Node = 'inst2'
                Info: Total cell delay = 2.180 ns ( 72.79 % )
                Info: Total interconnect delay = 0.815 ns ( 27.21 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: Clock "key3" Internal fmax is restricted to 275.03 MHz between source register "inst1" and destination register "inst1"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.849 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y2_N5; Fanout = 4; REG Node = 'inst1'
            Info: 2: + IC(0.540 ns) + CELL(0.309 ns) = 0.849 ns; Loc. = LC_X34_Y2_N5; Fanout = 4; REG Node = 'inst1'
            Info: Total cell delay = 0.309 ns ( 36.40 % )
            Info: Total interconnect delay = 0.540 ns ( 63.60 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "key3" to destination register is 2.986 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_123; Fanout = 1; CLK Node = 'key3'
                Info: 2: + IC(0.806 ns) + CELL(0.711 ns) = 2.986 ns; Loc. = LC_X34_Y2_N5; Fanout = 4; REG Node = 'inst1'
                Info: Total cell delay = 2.180 ns ( 73.01 % )
                Info: Total interconnect delay = 0.806 ns ( 26.99 % )
            Info: - Longest clock path from clock "key3" to source register is 2.986 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_123; Fanout = 1; CLK Node = 'key3'
                Info: 2: + IC(0.806 ns) + CELL(0.711 ns) = 2.986 ns; Loc. = LC_X34_Y2_N5; Fanout = 4; REG Node = 'inst1'
                Info: Total cell delay = 2.180 ns ( 73.01 % )
                Info: Total interconnect delay = 0.806 ns ( 26.99 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "key2" to destination pin "cout" through register "inst2" is 11.776 ns
    Info: + Longest clock path from clock "key2" to source register is 2.995 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_122; Fanout = 1; CLK Node = 'key2'
        Info: 2: + IC(0.815 ns) + CELL(0.711 ns) = 2.995 ns; Loc. = LC_X34_Y1_N2; Fanout = 4; REG Node = 'inst2'
        Info: Total cell delay = 2.180 ns ( 72.79 % )
        Info: Total interconnect delay = 0.815 ns ( 27.21 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 8.557 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y1_N2; Fanout = 4; REG Node = 'inst2'
        Info: 2: + IC(1.293 ns) + CELL(0.590 ns) = 1.883 ns; Loc. = LC_X34_Y2_N6; Fanout = 1; COMB Node = 'fulladd:inst|add~92'
        Info: 3: + IC(4.550 ns) + CELL(2.124 ns) = 8.557 ns; Loc. = PIN_49; Fanout = 0; PIN Node = 'cout'
        Info: Total cell delay = 2.714 ns ( 31.72 % )
        Info: Total interconnect delay = 5.843 ns ( 68.28 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Sep 15 16:56:14 2006
    Info: Elapsed time: 00:00:01