full_add.tan.qmsg

很多vhdl例程代码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "key3 register register inst1 inst1 275.03 MHz Internal " "Info: Clock \"key3\" Internal fmax is restricted to 275.03 MHz between source register \"inst1\" and destination register \"inst1\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.849 ns + Longest register register " "Info: + Longest register to register delay is 0.849 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst1 1 REG LC_X34_Y2_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y2_N5; Fanout = 4; REG Node = 'inst1'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "" { inst1 } "NODE_NAME" } "" } } { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 128 176 240 208 "inst1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.540 ns) + CELL(0.309 ns) 0.849 ns inst1 2 REG LC_X34_Y2_N5 4 " "Info: 2: + IC(0.540 ns) + CELL(0.309 ns) = 0.849 ns; Loc. = LC_X34_Y2_N5; Fanout = 4; REG Node = 'inst1'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "0.849 ns" { inst1 inst1 } "NODE_NAME" } "" } } { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 128 176 240 208 "inst1" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns 36.40 % " "Info: Total cell delay = 0.309 ns ( 36.40 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.540 ns 63.60 % " "Info: Total interconnect delay = 0.540 ns ( 63.60 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "0.849 ns" { inst1 inst1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.849 ns" { inst1 inst1 } { 0.000ns 0.540ns } { 0.000ns 0.309ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "key3 destination 2.986 ns + Shortest register " "Info: + Shortest clock path from clock \"key3\" to destination register is 2.986 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns key3 1 CLK PIN_123 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_123; Fanout = 1; CLK Node = 'key3'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "" { key3 } "NODE_NAME" } "" } } { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 296 -256 -88 312 "key3" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.806 ns) + CELL(0.711 ns) 2.986 ns inst1 2 REG LC_X34_Y2_N5 4 " "Info: 2: + IC(0.806 ns) + CELL(0.711 ns) = 2.986 ns; Loc. = LC_X34_Y2_N5; Fanout = 4; REG Node = 'inst1'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "1.517 ns" { key3 inst1 } "NODE_NAME" } "" } } { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 128 176 240 208 "inst1" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.01 % " "Info: Total cell delay = 2.180 ns ( 73.01 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.806 ns 26.99 % " "Info: Total interconnect delay = 0.806 ns ( 26.99 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "2.986 ns" { key3 inst1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.986 ns" { key3 key3~out0 inst1 } { 0.000ns 0.000ns 0.806ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "key3 source 2.986 ns - Longest register " "Info: - Longest clock path from clock \"key3\" to source register is 2.986 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns key3 1 CLK PIN_123 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_123; Fanout = 1; CLK Node = 'key3'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "" { key3 } "NODE_NAME" } "" } } { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 296 -256 -88 312 "key3" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.806 ns) + CELL(0.711 ns) 2.986 ns inst1 2 REG LC_X34_Y2_N5 4 " "Info: 2: + IC(0.806 ns) + CELL(0.711 ns) = 2.986 ns; Loc. = LC_X34_Y2_N5; Fanout = 4; REG Node = 'inst1'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "1.517 ns" { key3 inst1 } "NODE_NAME" } "" } } { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 128 176 240 208 "inst1" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.01 % " "Info: Total cell delay = 2.180 ns ( 73.01 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.806 ns 26.99 % " "Info: Total interconnect delay = 0.806 ns ( 26.99 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "2.986 ns" { key3 inst1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.986 ns" { key3 key3~out0 inst1 } { 0.000ns 0.000ns 0.806ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "2.986 ns" { key3 inst1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.986 ns" { key3 key3~out0 inst1 } { 0.000ns 0.000ns 0.806ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "2.986 ns" { key3 inst1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.986 ns" { key3 key3~out0 inst1 } { 0.000ns 0.000ns 0.806ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 128 176 240 208 "inst1" "" } } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 128 176 240 208 "inst1" "" } } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "0.849 ns" { inst1 inst1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.849 ns" { inst1 inst1 } { 0.000ns 0.540ns } { 0.000ns 0.309ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "2.986 ns" { key3 inst1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.986 ns" { key3 key3~out0 inst1 } { 0.000ns 0.000ns 0.806ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "2.986 ns" { key3 inst1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.986 ns" { key3 key3~out0 inst1 } { 0.000ns 0.000ns 0.806ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "" { inst1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { inst1 } {  } {  } } } { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 128 176 240 208 "inst1" "" } } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "key2 cout inst2 11.776 ns register " "Info: tco from clock \"key2\" to destination pin \"cout\" through register \"inst2\" is 11.776 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "key2 source 2.995 ns + Longest register " "Info: + Longest clock path from clock \"key2\" to source register is 2.995 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns key2 1 CLK PIN_122 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_122; Fanout = 1; CLK Node = 'key2'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "" { key2 } "NODE_NAME" } "" } } { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 248 -256 -88 264 "key2" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.815 ns) + CELL(0.711 ns) 2.995 ns inst2 2 REG LC_X34_Y1_N2 4 " "Info: 2: + IC(0.815 ns) + CELL(0.711 ns) = 2.995 ns; Loc. = LC_X34_Y1_N2; Fanout = 4; REG Node = 'inst2'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "1.526 ns" { key2 inst2 } "NODE_NAME" } "" } } { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 128 40 104 208 "inst2" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 72.79 % " "Info: Total cell delay = 2.180 ns ( 72.79 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.815 ns 27.21 % " "Info: Total interconnect delay = 0.815 ns ( 27.21 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "2.995 ns" { key2 inst2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.995 ns" { key2 key2~out0 inst2 } { 0.000ns 0.000ns 0.815ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 128 40 104 208 "inst2" "" } } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.557 ns + Longest register pin " "Info: + Longest register to pin delay is 8.557 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst2 1 REG LC_X34_Y1_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y1_N2; Fanout = 4; REG Node = 'inst2'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "" { inst2 } "NODE_NAME" } "" } } { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 128 40 104 208 "inst2" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.293 ns) + CELL(0.590 ns) 1.883 ns fulladd:inst\|add~92 2 COMB LC_X34_Y2_N6 1 " "Info: 2: + IC(1.293 ns) + CELL(0.590 ns) = 1.883 ns; Loc. = LC_X34_Y2_N6; Fanout = 1; COMB Node = 'fulladd:inst\|add~92'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "1.883 ns" { inst2 fulladd:inst|add~92 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.550 ns) + CELL(2.124 ns) 8.557 ns cout 3 PIN PIN_49 0 " "Info: 3: + IC(4.550 ns) + CELL(2.124 ns) = 8.557 ns; Loc. = PIN_49; Fanout = 0; PIN Node = 'cout'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "6.674 ns" { fulladd:inst|add~92 cout } "NODE_NAME" } "" } } { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 144 512 688 160 "cout" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.714 ns 31.72 % " "Info: Total cell delay = 2.714 ns ( 31.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.843 ns 68.28 % " "Info: Total interconnect delay = 5.843 ns ( 68.28 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "8.557 ns" { inst2 fulladd:inst|add~92 cout } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.557 ns" { inst2 fulladd:inst|add~92 cout } { 0.000ns 1.293ns 4.550ns } { 0.000ns 0.590ns 2.124ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "2.995 ns" { key2 inst2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.995 ns" { key2 key2~out0 inst2 } { 0.000ns 0.000ns 0.815ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "8.557 ns" { inst2 fulladd:inst|add~92 cout } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.557 ns" { inst2 fulladd:inst|add~92 cout } { 0.000ns 1.293ns 4.550ns } { 0.000ns 0.590ns 2.124ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 15 16:56:14 2006 " "Info: Processing ended: Fri Sep 15 16:56:14 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}