📄 full_add.tan.qmsg
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "key1 " "Info: Assuming node \"key1\" is an undefined clock" { } { { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 160 -256 -88 176 "key1" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "key1" } } } } } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "key2 " "Info: Assuming node \"key2\" is an undefined clock" { } { { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 248 -256 -88 264 "key2" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "key2" } } } } } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "key3 " "Info: Assuming node \"key3\" is an undefined clock" { } { { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 296 -256 -88 312 "key3" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "key3" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "key1 register register inst3 inst3 275.03 MHz Internal " "Info: Clock \"key1\" Internal fmax is restricted to 275.03 MHz between source register \"inst3\" and destination register \"inst3\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.041 ns + Longest register register " "Info: + Longest register to register delay is 1.041 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst3 1 REG LC_X34_Y2_N4 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y2_N4; Fanout = 4; REG Node = 'inst3'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "" { inst3 } "NODE_NAME" } "" } } { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 128 -88 -24 208 "inst3" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.563 ns) + CELL(0.478 ns) 1.041 ns inst3 2 REG LC_X34_Y2_N4 4 " "Info: 2: + IC(0.563 ns) + CELL(0.478 ns) = 1.041 ns; Loc. = LC_X34_Y2_N4; Fanout = 4; REG Node = 'inst3'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "1.041 ns" { inst3 inst3 } "NODE_NAME" } "" } } { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 128 -88 -24 208 "inst3" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.478 ns 45.92 % " "Info: Total cell delay = 0.478 ns ( 45.92 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.563 ns 54.08 % " "Info: Total interconnect delay = 0.563 ns ( 54.08 % )" { } { } 0} } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "1.041 ns" { inst3 inst3 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.041 ns" { inst3 inst3 } { 0.000ns 0.563ns } { 0.000ns 0.478ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "key1 destination 3.511 ns + Shortest register " "Info: + Shortest clock path from clock \"key1\" to destination register is 3.511 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns key1 1 CLK PIN_121 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_121; Fanout = 1; CLK Node = 'key1'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "" { key1 } "NODE_NAME" } "" } } { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 160 -256 -88 176 "key1" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.331 ns) + CELL(0.711 ns) 3.511 ns inst3 2 REG LC_X34_Y2_N4 4 " "Info: 2: + IC(1.331 ns) + CELL(0.711 ns) = 3.511 ns; Loc. = LC_X34_Y2_N4; Fanout = 4; REG Node = 'inst3'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "2.042 ns" { key1 inst3 } "NODE_NAME" } "" } } { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 128 -88 -24 208 "inst3" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 62.09 % " "Info: Total cell delay = 2.180 ns ( 62.09 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.331 ns 37.91 % " "Info: Total interconnect delay = 1.331 ns ( 37.91 % )" { } { } 0} } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "3.511 ns" { key1 inst3 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.511 ns" { key1 key1~out0 inst3 } { 0.000ns 0.000ns 1.331ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "key1 source 3.511 ns - Longest register " "Info: - Longest clock path from clock \"key1\" to source register is 3.511 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns key1 1 CLK PIN_121 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_121; Fanout = 1; CLK Node = 'key1'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "" { key1 } "NODE_NAME" } "" } } { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 160 -256 -88 176 "key1" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.331 ns) + CELL(0.711 ns) 3.511 ns inst3 2 REG LC_X34_Y2_N4 4 " "Info: 2: + IC(1.331 ns) + CELL(0.711 ns) = 3.511 ns; Loc. = LC_X34_Y2_N4; Fanout = 4; REG Node = 'inst3'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "2.042 ns" { key1 inst3 } "NODE_NAME" } "" } } { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 128 -88 -24 208 "inst3" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 62.09 % " "Info: Total cell delay = 2.180 ns ( 62.09 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.331 ns 37.91 % " "Info: Total interconnect delay = 1.331 ns ( 37.91 % )" { } { } 0} } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "3.511 ns" { key1 inst3 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.511 ns" { key1 key1~out0 inst3 } { 0.000ns 0.000ns 1.331ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "3.511 ns" { key1 inst3 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.511 ns" { key1 key1~out0 inst3 } { 0.000ns 0.000ns 1.331ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "3.511 ns" { key1 inst3 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.511 ns" { key1 key1~out0 inst3 } { 0.000ns 0.000ns 1.331ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 128 -88 -24 208 "inst3" "" } } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 128 -88 -24 208 "inst3" "" } } } } } 0} } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "1.041 ns" { inst3 inst3 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.041 ns" { inst3 inst3 } { 0.000ns 0.563ns } { 0.000ns 0.478ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "3.511 ns" { key1 inst3 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.511 ns" { key1 key1~out0 inst3 } { 0.000ns 0.000ns 1.331ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "3.511 ns" { key1 inst3 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.511 ns" { key1 key1~out0 inst3 } { 0.000ns 0.000ns 1.331ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "" { inst3 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { inst3 } { } { } } } { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 128 -88 -24 208 "inst3" "" } } } } } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "key2 register register inst2 inst2 275.03 MHz Internal " "Info: Clock \"key2\" Internal fmax is restricted to 275.03 MHz between source register \"inst2\" and destination register \"inst2\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.014 ns + Longest register register " "Info: + Longest register to register delay is 1.014 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst2 1 REG LC_X34_Y1_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y1_N2; Fanout = 4; REG Node = 'inst2'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "" { inst2 } "NODE_NAME" } "" } } { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 128 40 104 208 "inst2" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.536 ns) + CELL(0.478 ns) 1.014 ns inst2 2 REG LC_X34_Y1_N2 4 " "Info: 2: + IC(0.536 ns) + CELL(0.478 ns) = 1.014 ns; Loc. = LC_X34_Y1_N2; Fanout = 4; REG Node = 'inst2'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "1.014 ns" { inst2 inst2 } "NODE_NAME" } "" } } { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 128 40 104 208 "inst2" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.478 ns 47.14 % " "Info: Total cell delay = 0.478 ns ( 47.14 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.536 ns 52.86 % " "Info: Total interconnect delay = 0.536 ns ( 52.86 % )" { } { } 0} } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "1.014 ns" { inst2 inst2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.014 ns" { inst2 inst2 } { 0.000ns 0.536ns } { 0.000ns 0.478ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "key2 destination 2.995 ns + Shortest register " "Info: + Shortest clock path from clock \"key2\" to destination register is 2.995 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns key2 1 CLK PIN_122 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_122; Fanout = 1; CLK Node = 'key2'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "" { key2 } "NODE_NAME" } "" } } { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 248 -256 -88 264 "key2" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.815 ns) + CELL(0.711 ns) 2.995 ns inst2 2 REG LC_X34_Y1_N2 4 " "Info: 2: + IC(0.815 ns) + CELL(0.711 ns) = 2.995 ns; Loc. = LC_X34_Y1_N2; Fanout = 4; REG Node = 'inst2'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "1.526 ns" { key2 inst2 } "NODE_NAME" } "" } } { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 128 40 104 208 "inst2" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 72.79 % " "Info: Total cell delay = 2.180 ns ( 72.79 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.815 ns 27.21 % " "Info: Total interconnect delay = 0.815 ns ( 27.21 % )" { } { } 0} } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "2.995 ns" { key2 inst2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.995 ns" { key2 key2~out0 inst2 } { 0.000ns 0.000ns 0.815ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "key2 source 2.995 ns - Longest register " "Info: - Longest clock path from clock \"key2\" to source register is 2.995 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns key2 1 CLK PIN_122 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_122; Fanout = 1; CLK Node = 'key2'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "" { key2 } "NODE_NAME" } "" } } { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 248 -256 -88 264 "key2" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.815 ns) + CELL(0.711 ns) 2.995 ns inst2 2 REG LC_X34_Y1_N2 4 " "Info: 2: + IC(0.815 ns) + CELL(0.711 ns) = 2.995 ns; Loc. = LC_X34_Y1_N2; Fanout = 4; REG Node = 'inst2'" { } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "1.526 ns" { key2 inst2 } "NODE_NAME" } "" } } { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 128 40 104 208 "inst2" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 72.79 % " "Info: Total cell delay = 2.180 ns ( 72.79 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.815 ns 27.21 % " "Info: Total interconnect delay = 0.815 ns ( 27.21 % )" { } { } 0} } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "2.995 ns" { key2 inst2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.995 ns" { key2 key2~out0 inst2 } { 0.000ns 0.000ns 0.815ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "2.995 ns" { key2 inst2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.995 ns" { key2 key2~out0 inst2 } { 0.000ns 0.000ns 0.815ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "2.995 ns" { key2 inst2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.995 ns" { key2 key2~out0 inst2 } { 0.000ns 0.000ns 0.815ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 128 40 104 208 "inst2" "" } } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 128 40 104 208 "inst2" "" } } } } } 0} } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "1.014 ns" { inst2 inst2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.014 ns" { inst2 inst2 } { 0.000ns 0.536ns } { 0.000ns 0.478ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "2.995 ns" { key2 inst2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.995 ns" { key2 key2~out0 inst2 } { 0.000ns 0.000ns 0.815ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "2.995 ns" { key2 inst2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.995 ns" { key2 key2~out0 inst2 } { 0.000ns 0.000ns 0.815ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "" { inst2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { inst2 } { } { } } } { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 128 40 104 208 "inst2" "" } } } } } 0}
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