full_add.fit.qmsg

很多vhdl例程代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1.04 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1.04 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Sep 15 16:56:06 2006 " "Info: Processing started: Fri Sep 15 16:56:06 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off full_add -c full_add " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off full_add -c full_add" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "full_add EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"full_add\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "0.888 ns register register " "Info: Estimated most critical path is register to register delay of 0.888 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst3 1 REG LAB_X34_Y2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X34_Y2; Fanout = 4; REG Node = 'inst3'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "" { inst3 } "NODE_NAME" } "" } } { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 128 -88 -24 208 "inst3" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.150 ns) + CELL(0.738 ns) 0.888 ns inst3 2 REG LAB_X34_Y2 4 " "Info: 2: + IC(0.150 ns) + CELL(0.738 ns) = 0.888 ns; Loc. = LAB_X34_Y2; Fanout = 4; REG Node = 'inst3'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "0.888 ns" { inst3 inst3 } "NODE_NAME" } "" } } { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 128 -88 -24 208 "inst3" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns 83.11 % " "Info: Total cell delay = 0.738 ns ( 83.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.150 ns 16.89 % " "Info: Total interconnect delay = 0.150 ns ( 16.89 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add_cmp.qrpt" Compiler "full_add" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/db/full_add.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/" "" "0.888 ns" { inst3 inst3 } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 15 16:56:09 2006 " "Info: Processing ended: Fri Sep 15 16:56:09 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}