full_add.map.qmsg

很多vhdl例程代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1.04 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1.04 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Sep 15 16:56:03 2006 " "Info: Processing started: Fri Sep 15 16:56:03 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off full_add -c full_add " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off full_add -c full_add" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fulladd.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fulladd.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fulladd-one " "Info: Found design unit 1: fulladd-one" {  } { { "fulladd.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/fulladd.vhd" 34 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 fulladd " "Info: Found entity 1: fulladd" {  } { { "fulladd.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/fulladd.vhd" 27 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "full_add.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file full_add.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 full_add " "Info: Found entity 1: full_add" {  } { { "full_add.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "full_add " "Info: Elaborating entity \"full_add\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fulladd fulladd:inst " "Info: Elaborating entity \"fulladd\" for hierarchy \"fulladd:inst\"" {  } { { "full_add.bdf" "inst" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_7_full_add/full_add.bdf" { { 88 296 392 184 "inst" "" } } } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "13 " "Info: Implemented 13 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "5 " "Info: Implemented 5 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 15 16:56:04 2006 " "Info: Processing ended: Fri Sep 15 16:56:04 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}