key_debounce.fit.qmsg

很多vhdl例程代码

{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.584 ns register register " "Info: Estimated most critical path is register to register delay of 4.584 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst2\|Counter\[4\] 1 REG LAB_X8_Y10 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X8_Y10; Fanout = 5; REG Node = 'int_div:inst2\|Counter\[4\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "" { int_div:inst2|Counter[4] } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.177 ns) + CELL(0.575 ns) 1.752 ns int_div:inst2\|add~313COUT1_365 2 COMB LAB_X9_Y11 2 " "Info: 2: + IC(1.177 ns) + CELL(0.575 ns) = 1.752 ns; Loc. = LAB_X9_Y11; Fanout = 2; COMB Node = 'int_div:inst2\|add~313COUT1_365'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "1.752 ns" { int_div:inst2|Counter[4] int_div:inst2|add~313COUT1_365 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.832 ns int_div:inst2\|add~308COUT1_366 3 COMB LAB_X9_Y11 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.832 ns; Loc. = LAB_X9_Y11; Fanout = 2; COMB Node = 'int_div:inst2\|add~308COUT1_366'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "0.080 ns" { int_div:inst2|add~313COUT1_365 int_div:inst2|add~308COUT1_366 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.912 ns int_div:inst2\|add~343COUT1_367 4 COMB LAB_X9_Y11 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.912 ns; Loc. = LAB_X9_Y11; Fanout = 2; COMB Node = 'int_div:inst2\|add~343COUT1_367'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "0.080 ns" { int_div:inst2|add~308COUT1_366 int_div:inst2|add~343COUT1_367 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.992 ns int_div:inst2\|add~298COUT1_368 5 COMB LAB_X9_Y11 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.992 ns; Loc. = LAB_X9_Y11; Fanout = 2; COMB Node = 'int_div:inst2\|add~298COUT1_368'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "0.080 ns" { int_div:inst2|add~343COUT1_367 int_div:inst2|add~298COUT1_368 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 2.250 ns int_div:inst2\|add~303 6 COMB LAB_X9_Y11 6 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 2.250 ns; Loc. = LAB_X9_Y11; Fanout = 6; COMB Node = 'int_div:inst2\|add~303'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "0.258 ns" { int_div:inst2|add~298COUT1_368 int_div:inst2|add~303 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.386 ns int_div:inst2\|add~283 7 COMB LAB_X9_Y10 4 " "Info: 7: + IC(0.000 ns) + CELL(0.136 ns) = 2.386 ns; Loc. = LAB_X9_Y10; Fanout = 4; COMB Node = 'int_div:inst2\|add~283'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "0.136 ns" { int_div:inst2|add~303 int_div:inst2|add~283 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.679 ns) 3.065 ns int_div:inst2\|add~356 8 COMB LAB_X9_Y10 1 " "Info: 8: + IC(0.000 ns) + CELL(0.679 ns) = 3.065 ns; Loc. = LAB_X9_Y10; Fanout = 1; COMB Node = 'int_div:inst2\|add~356'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "0.679 ns" { int_div:inst2|add~283 int_div:inst2|add~356 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.781 ns) + CELL(0.738 ns) 4.584 ns int_div:inst2\|Counter\[17\] 9 REG LAB_X8_Y11 10 " "Info: 9: + IC(0.781 ns) + CELL(0.738 ns) = 4.584 ns; Loc. = LAB_X8_Y11; Fanout = 10; REG Node = 'int_div:inst2\|Counter\[17\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "1.519 ns" { int_div:inst2|add~356 int_div:inst2|Counter[17] } "NODE_NAME" } "" } } { "int_div.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/int_div.vhd" 37 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.626 ns 57.29 % " "Info: Total cell delay = 2.626 ns ( 57.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.958 ns 42.71 % " "Info: Total interconnect delay = 1.958 ns ( 42.71 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "4.584 ns" { int_div:inst2|Counter[4] int_div:inst2|add~313COUT1_365 int_div:inst2|add~308COUT1_366 int_div:inst2|add~343COUT1_367 int_div:inst2|add~298COUT1_368 int_div:inst2|add~303 int_div:inst2|add~283 int_div:inst2|add~356 int_div:inst2|Counter[17] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%." {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "9 " "Warning: The following 9 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "dig\[7\] GND " "Info: Pin dig\[7\] has GND driving its datain port" {  } { { "key_debounce.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.bdf" { { 184 496 672 200 "dig\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dig\[7\]" } } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "" { dig[7] } "NODE_NAME" } "" } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.fld" "" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.fld" "" "" { dig[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "dig\[6\] GND " "Info: Pin dig\[6\] has GND driving its datain port" {  } { { "key_debounce.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.bdf" { { 184 496 672 200 "dig\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dig\[6\]" } } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "" { dig[6] } "NODE_NAME" } "" } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.fld" "" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.fld" "" "" { dig[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "dig\[5\] GND " "Info: Pin dig\[5\] has GND driving its datain port" {  } { { "key_debounce.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.bdf" { { 184 496 672 200 "dig\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dig\[5\]" } } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "" { dig[5] } "NODE_NAME" } "" } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.fld" "" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.fld" "" "" { dig[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "dig\[4\] GND " "Info: Pin dig\[4\] has GND driving its datain port" {  } { { "key_debounce.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.bdf" { { 184 496 672 200 "dig\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dig\[4\]" } } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "" { dig[4] } "NODE_NAME" } "" } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.fld" "" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.fld" "" "" { dig[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "dig\[3\] GND " "Info: Pin dig\[3\] has GND driving its datain port" {  } { { "key_debounce.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.bdf" { { 184 496 672 200 "dig\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dig\[3\]" } } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "" { dig[3] } "NODE_NAME" } "" } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.fld" "" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.fld" "" "" { dig[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "dig\[2\] GND " "Info: Pin dig\[2\] has GND driving its datain port" {  } { { "key_debounce.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.bdf" { { 184 496 672 200 "dig\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dig\[2\]" } } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "" { dig[2] } "NODE_NAME" } "" } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.fld" "" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.fld" "" "" { dig[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "dig\[1\] GND " "Info: Pin dig\[1\] has GND driving its datain port" {  } { { "key_debounce.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.bdf" { { 184 496 672 200 "dig\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dig\[1\]" } } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "" { dig[1] } "NODE_NAME" } "" } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.fld" "" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.fld" "" "" { dig[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "dig\[0\] GND " "Info: Pin dig\[0\] has GND driving its datain port" {  } { { "key_debounce.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.bdf" { { 184 496 672 200 "dig\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "dig\[0\]" } } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "" { dig[0] } "NODE_NAME" } "" } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.fld" "" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.fld" "" "" { dig[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seg\[7\] VCC " "Info: Pin seg\[7\] has VCC driving its datain port" {  } { { "key_debounce.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.bdf" { { 304 552 728 320 "seg\[7..0\]" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "seg\[7\]" } } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "" { seg[7] } "NODE_NAME" } "" } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.fld" "" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.fld" "" "" { seg[7] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 20 09:05:11 2006 " "Info: Processing ended: Wed Sep 20 09:05:11 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0}  } {  } 0}