key_debounce.tan.qmsg

很多vhdl例程代码

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "inst5~29 " "Info: Detected gated clock \"inst5~29\" as buffer" {  } { { "key_debounce.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.bdf" { { 280 176 240 328 "inst5" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "inst5~29" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "debounce:inst\|dout1\[0\] register counter:inst3\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[1\] register counter:inst3\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[3\] 17.694 ns " "Info: Slack time is 17.694 ns for clock \"debounce:inst\|dout1\[0\]\" between source register \"counter:inst3\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[1\]\" and destination register \"counter:inst3\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[3\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT_RESTRICTED" "275.03 MHz " "Info: Fmax is restricted to 275.03 MHz due to tcl and tch limits" {  } {  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "19.739 ns + Largest register register " "Info: + Largest register to register requirement is 19.739 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.000 ns + " "Info: + Setup relationship between source and destination is 20.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 20.000 ns " "Info: + Latch edge is 20.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination debounce:inst\|dout1\[0\] 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"debounce:inst\|dout1\[0\]\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source debounce:inst\|dout1\[0\] 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"debounce:inst\|dout1\[0\]\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "debounce:inst\|dout1\[0\] destination 5.682 ns + Shortest register " "Info: + Shortest clock path from clock \"debounce:inst\|dout1\[0\]\" to destination register is 5.682 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns debounce:inst\|dout1\[0\] 1 CLK LC_X7_Y7_N5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y7_N5; Fanout = 2; CLK Node = 'debounce:inst\|dout1\[0\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "" { debounce:inst|dout1[0] } "NODE_NAME" } "" } } { "debounce.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/debounce.vhd" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.516 ns) + CELL(0.442 ns) 0.958 ns inst5~29 2 COMB LC_X7_Y7_N2 4 " "Info: 2: + IC(0.516 ns) + CELL(0.442 ns) = 0.958 ns; Loc. = LC_X7_Y7_N2; Fanout = 4; COMB Node = 'inst5~29'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "0.958 ns" { debounce:inst|dout1[0] inst5~29 } "NODE_NAME" } "" } } { "key_debounce.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.bdf" { { 280 176 240 328 "inst5" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.013 ns) + CELL(0.711 ns) 5.682 ns counter:inst3\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[3\] 3 REG LC_X34_Y16_N3 8 " "Info: 3: + IC(4.013 ns) + CELL(0.711 ns) = 5.682 ns; Loc. = LC_X34_Y16_N3; Fanout = 8; REG Node = 'counter:inst3\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[3\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "4.724 ns" { inst5~29 counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "db/cntr_cs6.tdf" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/cntr_cs6.tdf" 70 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.153 ns 20.29 % " "Info: Total cell delay = 1.153 ns ( 20.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.529 ns 79.71 % " "Info: Total interconnect delay = 4.529 ns ( 79.71 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "5.682 ns" { debounce:inst|dout1[0] inst5~29 counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.682 ns" { debounce:inst|dout1[0] inst5~29 counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } { 0.000ns 0.516ns 4.013ns } { 0.000ns 0.442ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "debounce:inst\|dout1\[0\] source 5.682 ns - Longest register " "Info: - Longest clock path from clock \"debounce:inst\|dout1\[0\]\" to source register is 5.682 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns debounce:inst\|dout1\[0\] 1 CLK LC_X7_Y7_N5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y7_N5; Fanout = 2; CLK Node = 'debounce:inst\|dout1\[0\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "" { debounce:inst|dout1[0] } "NODE_NAME" } "" } } { "debounce.vhd" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/debounce.vhd" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.516 ns) + CELL(0.442 ns) 0.958 ns inst5~29 2 COMB LC_X7_Y7_N2 4 " "Info: 2: + IC(0.516 ns) + CELL(0.442 ns) = 0.958 ns; Loc. = LC_X7_Y7_N2; Fanout = 4; COMB Node = 'inst5~29'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "0.958 ns" { debounce:inst|dout1[0] inst5~29 } "NODE_NAME" } "" } } { "key_debounce.bdf" "" { Schematic "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/key_debounce.bdf" { { 280 176 240 328 "inst5" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.013 ns) + CELL(0.711 ns) 5.682 ns counter:inst3\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[1\] 3 REG LC_X34_Y16_N1 10 " "Info: 3: + IC(4.013 ns) + CELL(0.711 ns) = 5.682 ns; Loc. = LC_X34_Y16_N1; Fanout = 10; REG Node = 'counter:inst3\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[1\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "4.724 ns" { inst5~29 counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "db/cntr_cs6.tdf" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/cntr_cs6.tdf" 70 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.153 ns 20.29 % " "Info: Total cell delay = 1.153 ns ( 20.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.529 ns 79.71 % " "Info: Total interconnect delay = 4.529 ns ( 79.71 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "5.682 ns" { debounce:inst|dout1[0] inst5~29 counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.682 ns" { debounce:inst|dout1[0] inst5~29 counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] } { 0.000ns 0.516ns 4.013ns } { 0.000ns 0.442ns 0.711ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "5.682 ns" { debounce:inst|dout1[0] inst5~29 counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.682 ns" { debounce:inst|dout1[0] inst5~29 counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } { 0.000ns 0.516ns 4.013ns } { 0.000ns 0.442ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "5.682 ns" { debounce:inst|dout1[0] inst5~29 counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.682 ns" { debounce:inst|dout1[0] inst5~29 counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] } { 0.000ns 0.516ns 4.013ns } { 0.000ns 0.442ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "db/cntr_cs6.tdf" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/cntr_cs6.tdf" 70 8 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "db/cntr_cs6.tdf" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/cntr_cs6.tdf" 70 8 0 } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "5.682 ns" { debounce:inst|dout1[0] inst5~29 counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.682 ns" { debounce:inst|dout1[0] inst5~29 counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } { 0.000ns 0.516ns 4.013ns } { 0.000ns 0.442ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "5.682 ns" { debounce:inst|dout1[0] inst5~29 counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.682 ns" { debounce:inst|dout1[0] inst5~29 counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] } { 0.000ns 0.516ns 4.013ns } { 0.000ns 0.442ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.045 ns - Longest register register " "Info: - Longest register to register delay is 2.045 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter:inst3\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[1\] 1 REG LC_X34_Y16_N1 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y16_N1; Fanout = 10; REG Node = 'counter:inst3\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[1\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "" { counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "db/cntr_cs6.tdf" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/cntr_cs6.tdf" 70 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.603 ns) + CELL(0.575 ns) 1.178 ns counter:inst3\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|counter_cella1~COUTCOUT1 2 COMB LC_X34_Y16_N1 2 " "Info: 2: + IC(0.603 ns) + CELL(0.575 ns) = 1.178 ns; Loc. = LC_X34_Y16_N1; Fanout = 2; COMB Node = 'counter:inst3\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|counter_cella1~COUTCOUT1'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "1.178 ns" { counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|counter_cella1~COUTCOUT1 } "NODE_NAME" } "" } } { "db/cntr_cs6.tdf" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/cntr_cs6.tdf" 39 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.258 ns counter:inst3\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|counter_cella2~COUTCOUT1_1 3 COMB LC_X34_Y16_N2 1 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.258 ns; Loc. = LC_X34_Y16_N2; Fanout = 1; COMB Node = 'counter:inst3\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|counter_cella2~COUTCOUT1_1'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "0.080 ns" { counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|counter_cella1~COUTCOUT1 counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|counter_cella2~COUTCOUT1_1 } "NODE_NAME" } "" } } { "db/cntr_cs6.tdf" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/cntr_cs6.tdf" 47 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.787 ns) 2.045 ns counter:inst3\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[3\] 4 REG LC_X34_Y16_N3 8 " "Info: 4: + IC(0.000 ns) + CELL(0.787 ns) = 2.045 ns; Loc. = LC_X34_Y16_N3; Fanout = 8; REG Node = 'counter:inst3\|lpm_counter:lpm_counter_component\|cntr_cs6:auto_generated\|safe_q\[3\]'" {  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "0.787 ns" { counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|counter_cella2~COUTCOUT1_1 counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "db/cntr_cs6.tdf" "" { Text "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/cntr_cs6.tdf" 70 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.442 ns 70.51 % " "Info: Total cell delay = 1.442 ns ( 70.51 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.603 ns 29.49 % " "Info: Total interconnect delay = 0.603 ns ( 29.49 % )" {  } {  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "2.045 ns" { counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|counter_cella1~COUTCOUT1 counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|counter_cella2~COUTCOUT1_1 counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.045 ns" { counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|counter_cella1~COUTCOUT1 counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|counter_cella2~COUTCOUT1_1 counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } { 0.000ns 0.603ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.787ns } } }  } 0}  } { { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "5.682 ns" { debounce:inst|dout1[0] inst5~29 counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.682 ns" { debounce:inst|dout1[0] inst5~29 counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } { 0.000ns 0.516ns 4.013ns } { 0.000ns 0.442ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "5.682 ns" { debounce:inst|dout1[0] inst5~29 counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.682 ns" { debounce:inst|dout1[0] inst5~29 counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] } { 0.000ns 0.516ns 4.013ns } { 0.000ns 0.442ns 0.711ns } } } { "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" "" { Report "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce_cmp.qrpt" Compiler "key_debounce" "UNKNOWN" "V1" "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/db/key_debounce.quartus_db" { Floorplan "E:/VHDL_soft/EDA/Example_VHDL/QuickSOPC_1C6/ep1c6_6_key_debounce/" "" "2.045 ns" { counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|counter_cella1~COUTCOUT1 counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|counter_cella2~COUTCOUT1_1 counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.045 ns" { counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[1] counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|counter_cella1~COUTCOUT1 counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|counter_cella2~COUTCOUT1_1 counter:inst3|lpm_counter:lpm_counter_component|cntr_cs6:auto_generated|safe_q[3] } { 0.000ns 0.603ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.787ns } } }  } 0}