gate.vhd

基于FLEX10K的频率计设计

LIBRARY	IEEE;
USE	IEEE.STD_LOGIC_1164.ALL;
USE	IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY GATE IS
	PORT(SEL1,SEL2,SEL3,TEST:IN STD_LOGIC;
		 TESTOUT:OUT STD_LOGIC);
END GATE;

ARCHITECTURE ONE OF GATE IS
SIGNAL CNTERA:INTEGER RANGE 0 TO 10#10#;  
SIGNAL CNTERB:INTEGER RANGE 0 TO 10#100#; 
BEGIN
SA:PROCESS(SEL1,TEST)IS  
   BEGIN 
	IF TEST'EVENT AND TEST='1' THEN IF SEL1 ='1'THEN TESTOUT<=TEST;
	  END IF;
	 END IF;	
   END PROCESS SA;

SBA:PROCESS(SEL2,TEST)  
	BEGIN
	IF TEST'EVENT AND TEST='1' THEN IF SEL2 ='1'
		THEN IF CNTERA=10#10#
			THEN CNTERA<=0;
				ELSE CNTERA<=CNTERA+1;
		END IF;
       END IF;
	  END IF;
    END PROCESS SBA;
SBB:PROCESS(CNTERA)IS
    BEGIN
	IF CNTERA=10#10# THEN TESTOUT<='1';
		ELSE TESTOUT<='0';
	END IF;
END PROCESS SBB;

SCA:PROCESS(SEL3,TEST) IS
	BEGIN
	IF TEST'EVENT AND TEST='1'
	 THEN IF SEL3='1' 
		THEN IF CNTERB=10#100#
			THEN CNTERB<=0;
				ELSE CNTERB<=CNTERB+1;
		END IF;
       END IF;
	  END IF;
    END PROCESS SCA;
SCB:PROCESS(CNTERB) IS
    BEGIN
	IF CNTERB=10#100# THEN TESTOUT<='1';
		ELSE TESTOUT<='0';END IF;
	END PROCESS SCB;
END ONE;