coutf6.rpt

基于FLEX10K的频率计设计

-- Node name is '|74390:45|:7' = '|74390:45|1QA' 
-- Equation name is '_LC2_A19', type is buried 
_LC2_A19 = DFFE(!_LC2_A19, !_LC1_A22, !_LC1_C18,  VCC,  VCC);

-- Node name is '|74390:45|:6' = '|74390:45|1QB' 
-- Equation name is '_LC6_B22', type is buried 
_LC6_B22 = DFFE(!_LC6_B22,  _LC2_B22, !_LC1_C18,  VCC,  VCC);

-- Node name is '|74390:45|:5' = '|74390:45|1QC' 
-- Equation name is '_LC3_B13', type is buried 
_LC3_B13 = DFFE(!_LC3_B13, !_LC6_B22, !_LC1_C18,  VCC,  VCC);

-- Node name is '|74390:45|:3' = '|74390:45|1QD' 
-- Equation name is '_LC4_B22', type is buried 
_LC4_B22 = DFFE( _EQ005, !_LC2_A19, !_LC1_C18,  VCC,  VCC);
  _EQ005 =  _LC3_B13 & !_LC4_B22 &  _LC6_B22;

-- Node name is '|74390:45|:34' = '|74390:45|2QA' 
-- Equation name is '_LC2_B13', type is buried 
_LC2_B13 = DFFE(!_LC2_B13, !_LC2_B11, !_LC1_C18,  VCC,  VCC);

-- Node name is '|74390:45|:33' = '|74390:45|2QB' 
-- Equation name is '_LC6_A22', type is buried 
_LC6_A22 = DFFE(!_LC6_A22,  _LC3_A22, !_LC1_C18,  VCC,  VCC);

-- Node name is '|74390:45|:32' = '|74390:45|2QC' 
-- Equation name is '_LC1_A24', type is buried 
_LC1_A24 = DFFE(!_LC1_A24, !_LC6_A22, !_LC1_C18,  VCC,  VCC);

-- Node name is '|74390:45|:31' = '|74390:45|2QD' 
-- Equation name is '_LC2_A22', type is buried 
_LC2_A22 = DFFE( _EQ006, !_LC2_B13, !_LC1_C18,  VCC,  VCC);
  _EQ006 =  _LC1_A24 & !_LC2_A22 &  _LC6_A22;

-- Node name is '|74390:45|:20' 
-- Equation name is '_LC2_B22', type is buried 
_LC2_B22 = LCELL( _EQ007);
  _EQ007 = !_LC2_A19
         #  _LC4_B22;

-- Node name is '|74390:45|:29' 
-- Equation name is '_LC3_A22', type is buried 
_LC3_A22 = LCELL( _EQ008);
  _EQ008 = !_LC2_B13
         #  _LC2_A22;

-- Node name is '|74390:46|:7' = '|74390:46|1QA' 
-- Equation name is '_LC8_B11', type is buried 
_LC8_B11 = DFFE(!_LC8_B11, !_LC2_B15, !_LC1_C18,  VCC,  VCC);

-- Node name is '|74390:46|:6' = '|74390:46|1QB' 
-- Equation name is '_LC6_B6', type is buried 
_LC6_B6  = DFFE(!_LC6_B6,  _LC3_B11, !_LC1_C18,  VCC,  VCC);

-- Node name is '|74390:46|:5' = '|74390:46|1QC' 
-- Equation name is '_LC2_B6', type is buried 
_LC2_B6  = DFFE(!_LC2_B6, !_LC6_B6, !_LC1_C18,  VCC,  VCC);

-- Node name is '|74390:46|:3' = '|74390:46|1QD' 
-- Equation name is '_LC1_B11', type is buried 
_LC1_B11 = DFFE( _EQ009, !_LC8_B11, !_LC1_C18,  VCC,  VCC);
  _EQ009 = !_LC1_B11 &  _LC2_B6 &  _LC6_B6;

-- Node name is '|74390:46|:34' = '|74390:46|2QA' 
-- Equation name is '_LC1_A19', type is buried 
_LC1_A19 = DFFE(!_LC1_A19, !_LC1_A20, !_LC1_C18,  VCC,  VCC);

-- Node name is '|74390:46|:33' = '|74390:46|2QB' 
-- Equation name is '_LC1_B15', type is buried 
_LC1_B15 = DFFE(!_LC1_B15,  _LC3_B15, !_LC1_C18,  VCC,  VCC);

-- Node name is '|74390:46|:32' = '|74390:46|2QC' 
-- Equation name is '_LC1_A17', type is buried 
_LC1_A17 = DFFE(!_LC1_A17, !_LC1_B15, !_LC1_C18,  VCC,  VCC);

-- Node name is '|74390:46|:31' = '|74390:46|2QD' 
-- Equation name is '_LC5_B15', type is buried 
_LC5_B15 = DFFE( _EQ010, !_LC1_A19, !_LC1_C18,  VCC,  VCC);
  _EQ010 =  _LC1_A17 &  _LC1_B15 & !_LC5_B15;

-- Node name is '|74390:46|:20' 
-- Equation name is '_LC3_B11', type is buried 
_LC3_B11 = LCELL( _EQ011);
  _EQ011 = !_LC8_B11
         #  _LC1_B11;

-- Node name is '|74390:46|:29' 
-- Equation name is '_LC3_B15', type is buried 
_LC3_B15 = LCELL( _EQ012);
  _EQ012 = !_LC1_A19
         #  _LC5_B15;

-- Node name is '|74390:47|:7' = '|74390:47|1QA' 
-- Equation name is '_LC6_A20', type is buried 
_LC6_A20 = DFFE(!_LC6_A20, !_LC1_A15, !_LC1_C18,  VCC,  VCC);

-- Node name is '|74390:47|:6' = '|74390:47|1QB' 
-- Equation name is '_LC3_A13', type is buried 
_LC3_A13 = DFFE(!_LC3_A13,  _LC8_A20, !_LC1_C18,  VCC,  VCC);

-- Node name is '|74390:47|:5' = '|74390:47|1QC' 
-- Equation name is '_LC2_A13', type is buried 
_LC2_A13 = DFFE(!_LC2_A13, !_LC3_A13, !_LC1_C18,  VCC,  VCC);

-- Node name is '|74390:47|:3' = '|74390:47|1QD' 
-- Equation name is '_LC5_A20', type is buried 
_LC5_A20 = DFFE( _EQ013, !_LC6_A20, !_LC1_C18,  VCC,  VCC);
  _EQ013 =  _LC2_A13 &  _LC3_A13 & !_LC5_A20;

-- Node name is '|74390:47|:34' = '|74390:47|2QA' 
-- Equation name is '_LC2_C18', type is buried 
_LC2_C18 = DFFE(!_LC2_C18, !_LC6_C18, !_LC1_C18,  VCC,  VCC);

-- Node name is '|74390:47|:33' = '|74390:47|2QB' 
-- Equation name is '_LC8_A15', type is buried 
_LC8_A15 = DFFE(!_LC8_A15,  _LC2_A15, !_LC1_C18,  VCC,  VCC);

-- Node name is '|74390:47|:32' = '|74390:47|2QC' 
-- Equation name is '_LC5_A17', type is buried 
_LC5_A17 = DFFE(!_LC5_A17, !_LC8_A15, !_LC1_C18,  VCC,  VCC);

-- Node name is '|74390:47|:31' = '|74390:47|2QD' 
-- Equation name is '_LC6_A15', type is buried 
_LC6_A15 = DFFE( _EQ014, !_LC2_C18, !_LC1_C18,  VCC,  VCC);
  _EQ014 =  _LC5_A17 & !_LC6_A15 &  _LC8_A15;

-- Node name is '|74390:47|:20' 
-- Equation name is '_LC8_A20', type is buried 
_LC8_A20 = LCELL( _EQ015);
  _EQ015 = !_LC6_A20
         #  _LC5_A20;

-- Node name is '|74390:47|:29' 
-- Equation name is '_LC2_A15', type is buried 
_LC2_A15 = LCELL( _EQ016);
  _EQ016 = !_LC2_C18
         #  _LC6_A15;

-- Node name is '~4~1' 
-- Equation name is '~4~1', location is LC3_B22, type is buried.
-- synthesized logic cell 
_LC3_B22 = LCELL( _EQ017);
  _EQ017 =  _LC2_A19 &  _LC2_A22 &  _LC2_B13 &  _LC4_B22;

-- Node name is '~4~2' 
-- Equation name is '~4~2', location is LC5_B22, type is buried.
-- synthesized logic cell 
_LC5_B22 = LCELL( _EQ018);
  _EQ018 =  _LC1_A19 &  _LC2_B11 &  _LC3_B22 &  _LC5_B15;

-- Node name is ':4' 
-- Equation name is '_LC1_B22', type is buried 
_LC1_B22 = LCELL( _EQ019);
  _EQ019 =  _LC1_A20 &  _LC2_C18 &  _LC5_B22 &  _LC6_A15;

-- Node name is ':33' 
-- Equation name is '_LC1_A22', type is buried 
!_LC1_A22 = _LC1_A22~NOT;
_LC1_A22~NOT = LCELL( _EQ020);
  _EQ020 = !_LC2_B13
         # !_LC2_A22;

-- Node name is ':34' 
-- Equation name is '_LC2_B11', type is buried 
!_LC2_B11 = _LC2_B11~NOT;
_LC2_B11~NOT = LCELL( _EQ021);
  _EQ021 = !_LC8_B11
         # !_LC1_B11;

-- Node name is ':35' 
-- Equation name is '_LC2_B15', type is buried 
!_LC2_B15 = _LC2_B15~NOT;
_LC2_B15~NOT = LCELL( _EQ022);
  _EQ022 = !_LC1_A19
         # !_LC5_B15;

-- Node name is ':36' 
-- Equation name is '_LC1_A20', type is buried 
!_LC1_A20 = _LC1_A20~NOT;
_LC1_A20~NOT = LCELL( _EQ023);
  _EQ023 = !_LC6_A20
         # !_LC5_A20;

-- Node name is ':37' 
-- Equation name is '_LC6_C18', type is buried 
!_LC6_C18 = _LC6_C18~NOT;
_LC6_C18~NOT = LCELL( _EQ024);
  _EQ024 = !test
         # !_LC3_C18;

-- Node name is ':38' 
-- Equation name is '_LC1_A15', type is buried 
!_LC1_A15 = _LC1_A15~NOT;
_LC1_A15~NOT = LCELL( _EQ025);
  _EQ025 = !_LC2_C18
         # !_LC6_A15;



Project Information                             d:\kechengshejitest\coutf6.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 15,574K