📄 coutf6.rpt
字号:
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\kechengshejitest\coutf6.rpt
coutf6
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - B 22 AND2 s 0 4 0 1 ~4~1
- 5 - B 22 AND2 s 0 4 0 1 ~4~2
- 1 - B 22 AND2 0 4 1 0 :4
- 1 - A 22 OR2 ! 0 2 0 1 :33
- 2 - B 11 OR2 ! 0 2 0 2 :34
- 2 - B 15 OR2 ! 0 2 0 1 :35
- 1 - A 20 OR2 ! 0 2 0 2 :36
- 6 - C 18 OR2 ! 1 1 0 1 :37
- 1 - A 15 OR2 ! 0 2 0 1 :38
- 4 - C 18 DFFE + 1 1 0 1 |74194:3|QD (|74194:3|:38)
- 3 - C 18 DFFE + 1 1 0 2 |74194:3|QC (|74194:3|:39)
- 1 - C 18 DFFE + 1 1 0 25 |74194:3|QB (|74194:3|:40)
- 5 - C 18 DFFE + 1 1 0 1 |74194:3|QA (|74194:3|:41)
- 4 - B 22 DFFE 0 4 1 2 |74390:45|1QD (|74390:45|:3)
- 3 - B 13 DFFE 0 2 1 1 |74390:45|1QC (|74390:45|:5)
- 6 - B 22 DFFE 0 2 1 2 |74390:45|1QB (|74390:45|:6)
- 2 - A 19 DFFE 0 2 1 3 |74390:45|1QA (|74390:45|:7)
- 2 - B 22 OR2 0 2 0 1 |74390:45|:20
- 3 - A 22 OR2 0 2 0 1 |74390:45|:29
- 2 - A 22 DFFE 0 4 1 3 |74390:45|2QD (|74390:45|:31)
- 1 - A 24 DFFE 0 2 1 1 |74390:45|2QC (|74390:45|:32)
- 6 - A 22 DFFE 0 2 1 2 |74390:45|2QB (|74390:45|:33)
- 2 - B 13 DFFE 0 2 1 4 |74390:45|2QA (|74390:45|:34)
- 1 - B 11 DFFE 0 4 1 2 |74390:46|1QD (|74390:46|:3)
- 2 - B 06 DFFE 0 2 1 1 |74390:46|1QC (|74390:46|:5)
- 6 - B 06 DFFE 0 2 1 2 |74390:46|1QB (|74390:46|:6)
- 8 - B 11 DFFE 0 2 1 3 |74390:46|1QA (|74390:46|:7)
- 3 - B 11 OR2 0 2 0 1 |74390:46|:20
- 3 - B 15 OR2 0 2 0 1 |74390:46|:29
- 5 - B 15 DFFE 0 4 1 3 |74390:46|2QD (|74390:46|:31)
- 1 - A 17 DFFE 0 2 1 1 |74390:46|2QC (|74390:46|:32)
- 1 - B 15 DFFE 0 2 1 2 |74390:46|2QB (|74390:46|:33)
- 1 - A 19 DFFE 0 2 1 4 |74390:46|2QA (|74390:46|:34)
- 5 - A 20 DFFE 0 4 1 2 |74390:47|1QD (|74390:47|:3)
- 2 - A 13 DFFE 0 2 1 1 |74390:47|1QC (|74390:47|:5)
- 3 - A 13 DFFE 0 2 1 2 |74390:47|1QB (|74390:47|:6)
- 6 - A 20 DFFE 0 2 1 3 |74390:47|1QA (|74390:47|:7)
- 8 - A 20 OR2 0 2 0 1 |74390:47|:20
- 2 - A 15 OR2 0 2 0 1 |74390:47|:29
- 6 - A 15 DFFE 0 4 1 3 |74390:47|2QD (|74390:47|:31)
- 5 - A 17 DFFE 0 2 1 1 |74390:47|2QC (|74390:47|:32)
- 8 - A 15 DFFE 0 2 1 2 |74390:47|2QB (|74390:47|:33)
- 2 - C 18 DFFE 0 2 1 4 |74390:47|2QA (|74390:47|:34)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\kechengshejitest\coutf6.rpt
coutf6
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 11/ 96( 11%) 0/ 48( 0%) 9/ 48( 18%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
B: 12/ 96( 12%) 3/ 48( 6%) 8/ 48( 16%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\kechengshejitest\coutf6.rpt
coutf6
** CLOCK SIGNALS **
Type Fan-out Name
DFF 6 |74390:47|2QA
DFF 6 |74390:46|2QA
DFF 6 |74390:45|2QA
DFF 5 |74390:45|1QA
DFF 5 |74390:47|1QA
DFF 5 |74390:46|1QA
DFF 4 |74390:45|2QB
DFF 4 |74390:45|1QB
DFF 4 |74390:47|1QB
DFF 4 |74390:46|1QB
INPUT 4 clk
DFF 4 |74390:47|2QB
DFF 4 |74390:46|2QB
LCELL 2 :34
LCELL 2 :36
LCELL 1 |74390:47|:20
LCELL 1 |74390:47|:29
LCELL 1 |74390:46|:29
LCELL 1 :33
LCELL 1 |74390:46|:20
LCELL 1 :35
LCELL 1 |74390:45|:29
LCELL 1 |74390:45|:20
LCELL 1 :37
LCELL 1 :38
Device-Specific Information: d:\kechengshejitest\coutf6.rpt
coutf6
** CLEAR SIGNALS **
Type Fan-out Name
DFF 25 |74194:3|QB
Device-Specific Information: d:\kechengshejitest\coutf6.rpt
coutf6
** EQUATIONS **
clk : INPUT;
start : INPUT;
test : INPUT;
-- Node name is 'a1'
-- Equation name is 'a1', type is output
a1 = _LC2_C18;
-- Node name is 'a2'
-- Equation name is 'a2', type is output
a2 = _LC6_A20;
-- Node name is 'a3'
-- Equation name is 'a3', type is output
a3 = _LC1_A19;
-- Node name is 'a4'
-- Equation name is 'a4', type is output
a4 = _LC8_B11;
-- Node name is 'a5'
-- Equation name is 'a5', type is output
a5 = _LC2_B13;
-- Node name is 'a6'
-- Equation name is 'a6', type is output
a6 = _LC2_A19;
-- Node name is 'b1'
-- Equation name is 'b1', type is output
b1 = _LC8_A15;
-- Node name is 'b2'
-- Equation name is 'b2', type is output
b2 = _LC3_A13;
-- Node name is 'b3'
-- Equation name is 'b3', type is output
b3 = _LC1_B15;
-- Node name is 'b4'
-- Equation name is 'b4', type is output
b4 = _LC6_B6;
-- Node name is 'b5'
-- Equation name is 'b5', type is output
b5 = _LC6_A22;
-- Node name is 'b6'
-- Equation name is 'b6', type is output
b6 = _LC6_B22;
-- Node name is 'c1'
-- Equation name is 'c1', type is output
c1 = _LC5_A17;
-- Node name is 'c2'
-- Equation name is 'c2', type is output
c2 = _LC2_A13;
-- Node name is 'c3'
-- Equation name is 'c3', type is output
c3 = _LC1_A17;
-- Node name is 'c4'
-- Equation name is 'c4', type is output
c4 = _LC2_B6;
-- Node name is 'c5'
-- Equation name is 'c5', type is output
c5 = _LC1_A24;
-- Node name is 'c6'
-- Equation name is 'c6', type is output
c6 = _LC3_B13;
-- Node name is 'd1'
-- Equation name is 'd1', type is output
d1 = _LC6_A15;
-- Node name is 'd2'
-- Equation name is 'd2', type is output
d2 = _LC5_A20;
-- Node name is 'd3'
-- Equation name is 'd3', type is output
d3 = _LC5_B15;
-- Node name is 'd4'
-- Equation name is 'd4', type is output
d4 = _LC1_B11;
-- Node name is 'd5'
-- Equation name is 'd5', type is output
d5 = _LC2_A22;
-- Node name is 'd6'
-- Equation name is 'd6', type is output
d6 = _LC4_B22;
-- Node name is 'over'
-- Equation name is 'over', type is output
over = _LC1_B22;
-- Node name is '|74194:3|:41' = '|74194:3|QA'
-- Equation name is '_LC5_C18', type is buried
_LC5_C18 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = _LC4_C18
# start;
-- Node name is '|74194:3|:40' = '|74194:3|QB'
-- Equation name is '_LC1_C18', type is buried
_LC1_C18 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC5_C18 & !start;
-- Node name is '|74194:3|:39' = '|74194:3|QC'
-- Equation name is '_LC3_C18', type is buried
_LC3_C18 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = _LC1_C18 & !start;
-- Node name is '|74194:3|:38' = '|74194:3|QD'
-- Equation name is '_LC4_C18', type is buried
_LC4_C18 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC3_C18 & !start;
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