mux4.vhd

来自「基于FLEX10K的频率计设计」· VHDL 代码 · 共 24 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX4 IS
PORT(I0,I1,I2,I3,A,B:IN STD_LOGIC;
	 Y:OUT STD_LOGIC);
END MUX4;
ARCHITECTURE ONE OF MUX4 IS
BEGIN
PROCESS(I0,I1,I2,I3,A,B)
VARIABLE MUXVAL:INTEGER RANGE 7 DOWNTO 0;
BEGIN
MUXVAL:=0;
IF (A='1')THEN MUXVAL:=MUXVAL+1;END IF;
IF (B='1')THEN MUXVAL:=MUXVAL+2;END IF;
CASE MUXVAL IS
	WHEN 0 =>Y<= I0;
	WHEN 1 =>Y<= I1;
	WHEN 2 =>Y<= I2;
	WHEN 3 =>Y<= I3;
	WHEN OTHERS => NULL;
END CASE;
END PROCESS;
END ONE;