cgate.rpt

来自「基于FLEX10K的频率计设计」· RPT 代码 · 共 1,047 行 · 第 1/4 页

RPT
1,047
字号
-- Node name is '|coutf6:64|74194:3|:39' = '|coutf6:64|74194:3|QC' 
-- Equation name is '_LC1_C26', type is buried 
_LC1_C26 = DFFE( _EQ022, GLOBAL( clk0),  VCC,  VCC,  VCC);
  _EQ022 =  _LC2_C26 & !start;

-- Node name is '|coutf6:64|74194:3|:38' = '|coutf6:64|74194:3|QD' 
-- Equation name is '_LC3_C26', type is buried 
_LC3_C26 = DFFE( _EQ023, GLOBAL( clk0),  VCC,  VCC,  VCC);
  _EQ023 =  _LC1_C26 & !start;

-- Node name is '|coutf6:64|74390:45|:7' = '|coutf6:64|74390:45|1QA' 
-- Equation name is '_LC7_F27', type is buried 
_LC7_F27 = DFFE(!_LC7_F27, !_LC2_F31, !_LC2_C26,  VCC,  VCC);

-- Node name is '|coutf6:64|74390:45|:6' = '|coutf6:64|74390:45|1QB' 
-- Equation name is '_LC2_F2', type is buried 
_LC2_F2  = DFFE(!_LC2_F2,  _LC6_F2, !_LC2_C26,  VCC,  VCC);

-- Node name is '|coutf6:64|74390:45|:5' = '|coutf6:64|74390:45|1QC' 
-- Equation name is '_LC4_F18', type is buried 
_LC4_F18 = DFFE(!_LC4_F18, !_LC2_F2, !_LC2_C26,  VCC,  VCC);

-- Node name is '|coutf6:64|74390:45|:3' = '|coutf6:64|74390:45|1QD' 
-- Equation name is '_LC3_F2', type is buried 
_LC3_F2  = DFFE( _EQ024, !_LC7_F27, !_LC2_C26,  VCC,  VCC);
  _EQ024 =  _LC2_F2 & !_LC3_F2 &  _LC4_F18;

-- Node name is '|coutf6:64|74390:45|:34' = '|coutf6:64|74390:45|2QA' 
-- Equation name is '_LC1_F18', type is buried 
_LC1_F18 = DFFE(!_LC1_F18, !_LC1_D5, !_LC2_C26,  VCC,  VCC);

-- Node name is '|coutf6:64|74390:45|:33' = '|coutf6:64|74390:45|2QB' 
-- Equation name is '_LC1_F31', type is buried 
_LC1_F31 = DFFE(!_LC1_F31,  _LC3_F31, !_LC2_C26,  VCC,  VCC);

-- Node name is '|coutf6:64|74390:45|:32' = '|coutf6:64|74390:45|2QC' 
-- Equation name is '_LC1_D34', type is buried 
_LC1_D34 = DFFE(!_LC1_D34, !_LC1_F31, !_LC2_C26,  VCC,  VCC);

-- Node name is '|coutf6:64|74390:45|:31' = '|coutf6:64|74390:45|2QD' 
-- Equation name is '_LC5_F31', type is buried 
_LC5_F31 = DFFE( _EQ025, !_LC1_F18, !_LC2_C26,  VCC,  VCC);
  _EQ025 =  _LC1_D34 &  _LC1_F31 & !_LC5_F31;

-- Node name is '|coutf6:64|74390:45|:20' 
-- Equation name is '_LC6_F2', type is buried 
_LC6_F2  = LCELL( _EQ026);
  _EQ026 = !_LC7_F27
         #  _LC3_F2;

-- Node name is '|coutf6:64|74390:45|:29' 
-- Equation name is '_LC3_F31', type is buried 
_LC3_F31 = LCELL( _EQ027);
  _EQ027 = !_LC1_F18
         #  _LC5_F31;

-- Node name is '|coutf6:64|74390:46|:7' = '|coutf6:64|74390:46|1QA' 
-- Equation name is '_LC8_D5', type is buried 
_LC8_D5  = DFFE(!_LC8_D5, !_LC2_D8, !_LC2_C26,  VCC,  VCC);

-- Node name is '|coutf6:64|74390:46|:6' = '|coutf6:64|74390:46|1QB' 
-- Equation name is '_LC3_D7', type is buried 
_LC3_D7  = DFFE(!_LC3_D7,  _LC5_D5, !_LC2_C26,  VCC,  VCC);

-- Node name is '|coutf6:64|74390:46|:5' = '|coutf6:64|74390:46|1QC' 
-- Equation name is '_LC6_D7', type is buried 
_LC6_D7  = DFFE(!_LC6_D7, !_LC3_D7, !_LC2_C26,  VCC,  VCC);

-- Node name is '|coutf6:64|74390:46|:3' = '|coutf6:64|74390:46|1QD' 
-- Equation name is '_LC6_D5', type is buried 
_LC6_D5  = DFFE( _EQ028, !_LC8_D5, !_LC2_C26,  VCC,  VCC);
  _EQ028 =  _LC3_D7 & !_LC6_D5 &  _LC6_D7;

-- Node name is '|coutf6:64|74390:46|:34' = '|coutf6:64|74390:46|2QA' 
-- Equation name is '_LC2_C7', type is buried 
_LC2_C7  = DFFE(!_LC2_C7, !_LC1_C7, !_LC2_C26,  VCC,  VCC);

-- Node name is '|coutf6:64|74390:46|:33' = '|coutf6:64|74390:46|2QB' 
-- Equation name is '_LC1_D8', type is buried 
_LC1_D8  = DFFE(!_LC1_D8,  _LC4_D8, !_LC2_C26,  VCC,  VCC);

-- Node name is '|coutf6:64|74390:46|:32' = '|coutf6:64|74390:46|2QC' 
-- Equation name is '_LC4_D34', type is buried 
_LC4_D34 = DFFE(!_LC4_D34, !_LC1_D8, !_LC2_C26,  VCC,  VCC);

-- Node name is '|coutf6:64|74390:46|:31' = '|coutf6:64|74390:46|2QD' 
-- Equation name is '_LC3_D8', type is buried 
_LC3_D8  = DFFE( _EQ029, !_LC2_C7, !_LC2_C26,  VCC,  VCC);
  _EQ029 =  _LC1_D8 & !_LC3_D8 &  _LC4_D34;

-- Node name is '|coutf6:64|74390:46|:20' 
-- Equation name is '_LC5_D5', type is buried 
_LC5_D5  = LCELL( _EQ030);
  _EQ030 =  _LC6_D5
         # !_LC8_D5;

-- Node name is '|coutf6:64|74390:46|:29' 
-- Equation name is '_LC4_D8', type is buried 
_LC4_D8  = LCELL( _EQ031);
  _EQ031 =  _LC3_D8
         # !_LC2_C7;

-- Node name is '|coutf6:64|74390:47|:7' = '|coutf6:64|74390:47|1QA' 
-- Equation name is '_LC5_F17', type is buried 
_LC5_F17 = DFFE(!_LC5_F17, !_LC2_F11, !_LC2_C26,  VCC,  VCC);

-- Node name is '|coutf6:64|74390:47|:6' = '|coutf6:64|74390:47|1QB' 
-- Equation name is '_LC8_C7', type is buried 
_LC8_C7  = DFFE(!_LC8_C7,  _LC3_C7, !_LC2_C26,  VCC,  VCC);

-- Node name is '|coutf6:64|74390:47|:5' = '|coutf6:64|74390:47|1QC' 
-- Equation name is '_LC4_C4', type is buried 
_LC4_C4  = DFFE(!_LC4_C4, !_LC8_C7, !_LC2_C26,  VCC,  VCC);

-- Node name is '|coutf6:64|74390:47|:3' = '|coutf6:64|74390:47|1QD' 
-- Equation name is '_LC5_C4', type is buried 
_LC5_C4  = DFFE( _EQ032, !_LC5_F17, !_LC2_C26,  VCC,  VCC);
  _EQ032 =  _LC4_C4 & !_LC5_C4 &  _LC8_C7;

-- Node name is '|coutf6:64|74390:47|:34' = '|coutf6:64|74390:47|2QA' 
-- Equation name is '_LC4_C26', type is buried 
_LC4_C26 = DFFE(!_LC4_C26, !_LC8_C26, !_LC2_C26,  VCC,  VCC);

-- Node name is '|coutf6:64|74390:47|:33' = '|coutf6:64|74390:47|2QB' 
-- Equation name is '_LC6_F11', type is buried 
_LC6_F11 = DFFE(!_LC6_F11,  _LC3_F11, !_LC2_C26,  VCC,  VCC);

-- Node name is '|coutf6:64|74390:47|:32' = '|coutf6:64|74390:47|2QC' 
-- Equation name is '_LC8_F17', type is buried 
_LC8_F17 = DFFE(!_LC8_F17, !_LC6_F11, !_LC2_C26,  VCC,  VCC);

-- Node name is '|coutf6:64|74390:47|:31' = '|coutf6:64|74390:47|2QD' 
-- Equation name is '_LC1_F11', type is buried 
_LC1_F11 = DFFE( _EQ033, !_LC4_C26, !_LC2_C26,  VCC,  VCC);
  _EQ033 = !_LC1_F11 &  _LC6_F11 &  _LC8_F17;

-- Node name is '|coutf6:64|74390:47|:20' 
-- Equation name is '_LC3_C7', type is buried 
_LC3_C7  = LCELL( _EQ034);
  _EQ034 =  _LC5_C4
         # !_LC5_F17;

-- Node name is '|coutf6:64|74390:47|:29' 
-- Equation name is '_LC3_F11', type is buried 
_LC3_F11 = LCELL( _EQ035);
  _EQ035 =  _LC1_F11
         # !_LC4_C26;

-- Node name is '|MUX4:5|~139~1' 
-- Equation name is '_LC1_C25', type is buried 
-- synthesized logic cell 
_LC1_C25 = LCELL( _EQ036);
  _EQ036 = !_LC1_C22 &  _LC1_C31 &  _LC3_C22
         #  _LC1_C22 &  _LC1_C31 & !_LC3_C22 &  _LC5_C25;

-- Node name is '|MUX4:5|~139~2' 
-- Equation name is '_LC6_C26', type is buried 
-- synthesized logic cell 
_LC6_C26 = LCELL( _EQ037);
  _EQ037 =  _LC1_C22 &  _LC1_C25
         #  _LC1_C25 &  _LC3_C22;

-- Node name is '|MUX4:5|:139' 
-- Equation name is '_LC7_C26', type is buried 
_LC7_C26 = LCELL( _EQ038);
  _EQ038 =  _LC6_C26
         # !_LC1_C22 & !_LC3_C22 &  test;



Project Information                              d:\kechengshejitest\cgate.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:02
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:06


Memory Allocated
-----------------

Peak memory allocated during compilation  = 23,432K

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