cgate.rpt
来自「基于FLEX10K的频率计设计」· RPT 代码 · 共 1,047 行 · 第 1/4 页
RPT
1,047 行
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\kechengshejitest\cgate.rpt
cgate
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
14 - - C -- OUTPUT 0 1 0 0 a1
122 - - - 18 OUTPUT 0 1 0 0 a2
117 - - - 08 OUTPUT 0 1 0 0 a3
88 - - D -- OUTPUT 0 1 0 0 a4
30 - - F -- OUTPUT 0 1 0 0 a5
33 - - F -- OUTPUT 0 1 0 0 a6
79 - - F -- OUTPUT 0 1 0 0 b1
95 - - C -- OUTPUT 0 1 0 0 b2
92 - - D -- OUTPUT 0 1 0 0 b3
91 - - D -- OUTPUT 0 1 0 0 b4
41 - - - 31 OUTPUT 0 1 0 0 b5
81 - - F -- OUTPUT 0 1 0 0 b6
78 - - F -- OUTPUT 0 1 0 0 c1
96 - - C -- OUTPUT 0 1 0 0 c2
21 - - D -- OUTPUT 0 1 0 0 c3
22 - - D -- OUTPUT 0 1 0 0 c4
141 - - - 33 OUTPUT 0 1 0 0 c5
80 - - F -- OUTPUT 0 1 0 0 c6
82 - - F -- OUTPUT 0 1 0 0 d1
17 - - C -- OUTPUT 0 1 0 0 d2
68 - - - 07 OUTPUT 0 1 0 0 d3
89 - - D -- OUTPUT 0 1 0 0 d4
32 - - F -- OUTPUT 0 1 0 0 d5
31 - - F -- OUTPUT 0 1 0 0 d6
97 - - C -- OUTPUT 0 1 0 0 over
18 - - C -- OUTPUT 0 1 0 0 s2
12 - - C -- OUTPUT 0 1 0 0 s3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\kechengshejitest\cgate.rpt
cgate
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - C 31 OR2 ! 0 4 0 2 |cnt10_100:52|co10 (|cnt10_100:52|:13)
- 4 - C 31 DFFE 0 3 0 2 |cnt10_100:52|74390:14|1QD (|cnt10_100:52|74390:14|:3)
- 3 - C 31 DFFE 0 1 0 2 |cnt10_100:52|74390:14|1QC (|cnt10_100:52|74390:14|:5)
- 2 - C 32 DFFE 0 1 0 3 |cnt10_100:52|74390:14|1QB (|cnt10_100:52|74390:14|:6)
- 1 - C 33 DFFE + 0 0 0 3 |cnt10_100:52|74390:14|1QA (|cnt10_100:52|74390:14|:7)
- 2 - C 31 OR2 0 2 0 1 |cnt10_100:52|74390:14|:20
- 4 - C 25 OR2 0 2 0 1 |cnt10_100:52|74390:14|:29
- 3 - C 25 DFFE 0 3 0 2 |cnt10_100:52|74390:14|2QD (|cnt10_100:52|74390:14|:31)
- 2 - C 35 DFFE 0 1 0 2 |cnt10_100:52|74390:14|2QC (|cnt10_100:52|74390:14|:32)
- 1 - C 35 DFFE 0 1 0 3 |cnt10_100:52|74390:14|2QB (|cnt10_100:52|74390:14|:33)
- 2 - C 25 DFFE 0 1 0 3 |cnt10_100:52|74390:14|2QA (|cnt10_100:52|74390:14|:34)
- 6 - C 22 DFFE 0 3 1 0 |CONTROL:50|:4
- 2 - C 22 DFFE 0 3 1 0 |CONTROL:50|:6
- 1 - C 22 DFFE 0 2 0 6 |CONTROL:50|SSEL1 (|CONTROL:50|:8)
- 3 - C 22 DFFE 0 2 0 6 |CONTROL:50|SSEL0 (|CONTROL:50|:9)
- 5 - C 25 AND2 s 0 4 0 1 |CONTROL:50|~83~1
- 1 - F 02 AND2 s 0 4 0 1 |coutf6:64|over~1 (|coutf6:64|~4~1)
- 5 - F 02 AND2 s 0 4 0 1 |coutf6:64|over~2 (|coutf6:64|~4~2)
- 4 - F 02 AND2 0 4 1 4 |coutf6:64|over (|coutf6:64|:4)
- 2 - F 31 AND2 0 2 0 1 |coutf6:64|:33
- 1 - D 05 AND2 0 2 0 2 |coutf6:64|:34
- 2 - D 08 AND2 0 2 0 1 |coutf6:64|:35
- 1 - C 07 AND2 0 2 0 1 |coutf6:64|:36
- 8 - C 26 OR2 ! 0 2 0 1 |coutf6:64|:37
- 2 - F 11 AND2 0 2 0 2 |coutf6:64|:38
- 3 - C 26 DFFE + 1 1 0 1 |coutf6:64|74194:3|QD (|coutf6:64|74194:3|:38)
- 1 - C 26 DFFE + 1 1 0 2 |coutf6:64|74194:3|QC (|coutf6:64|74194:3|:39)
- 2 - C 26 DFFE + 1 1 0 25 |coutf6:64|74194:3|QB (|coutf6:64|74194:3|:40)
- 5 - C 26 DFFE + 1 1 0 1 |coutf6:64|74194:3|QA (|coutf6:64|74194:3|:41)
- 3 - F 02 DFFE 0 4 1 2 |coutf6:64|74390:45|1QD (|coutf6:64|74390:45|:3)
- 4 - F 18 DFFE 0 2 1 1 |coutf6:64|74390:45|1QC (|coutf6:64|74390:45|:5)
- 2 - F 02 DFFE 0 2 1 2 |coutf6:64|74390:45|1QB (|coutf6:64|74390:45|:6)
- 7 - F 27 DFFE 0 2 1 3 |coutf6:64|74390:45|1QA (|coutf6:64|74390:45|:7)
- 6 - F 02 OR2 0 2 0 1 |coutf6:64|74390:45|:20
- 3 - F 31 OR2 0 2 0 1 |coutf6:64|74390:45|:29
- 5 - F 31 DFFE 0 4 1 3 |coutf6:64|74390:45|2QD (|coutf6:64|74390:45|:31)
- 1 - D 34 DFFE 0 2 1 1 |coutf6:64|74390:45|2QC (|coutf6:64|74390:45|:32)
- 1 - F 31 DFFE 0 2 1 2 |coutf6:64|74390:45|2QB (|coutf6:64|74390:45|:33)
- 1 - F 18 DFFE 0 2 1 4 |coutf6:64|74390:45|2QA (|coutf6:64|74390:45|:34)
- 6 - D 05 DFFE 0 4 1 2 |coutf6:64|74390:46|1QD (|coutf6:64|74390:46|:3)
- 6 - D 07 DFFE 0 2 1 1 |coutf6:64|74390:46|1QC (|coutf6:64|74390:46|:5)
- 3 - D 07 DFFE 0 2 1 2 |coutf6:64|74390:46|1QB (|coutf6:64|74390:46|:6)
- 8 - D 05 DFFE 0 2 1 3 |coutf6:64|74390:46|1QA (|coutf6:64|74390:46|:7)
- 5 - D 05 OR2 0 2 0 1 |coutf6:64|74390:46|:20
- 4 - D 08 OR2 0 2 0 1 |coutf6:64|74390:46|:29
- 3 - D 08 DFFE 0 4 1 3 |coutf6:64|74390:46|2QD (|coutf6:64|74390:46|:31)
- 4 - D 34 DFFE 0 2 1 1 |coutf6:64|74390:46|2QC (|coutf6:64|74390:46|:32)
- 1 - D 08 DFFE 0 2 1 2 |coutf6:64|74390:46|2QB (|coutf6:64|74390:46|:33)
- 2 - C 07 DFFE 0 2 1 4 |coutf6:64|74390:46|2QA (|coutf6:64|74390:46|:34)
- 5 - C 04 DFFE 0 4 1 3 |coutf6:64|74390:47|1QD (|coutf6:64|74390:47|:3)
- 4 - C 04 DFFE 0 2 1 1 |coutf6:64|74390:47|1QC (|coutf6:64|74390:47|:5)
- 8 - C 07 DFFE 0 2 1 2 |coutf6:64|74390:47|1QB (|coutf6:64|74390:47|:6)
- 5 - F 17 DFFE 0 2 1 4 |coutf6:64|74390:47|1QA (|coutf6:64|74390:47|:7)
- 3 - C 07 OR2 0 2 0 1 |coutf6:64|74390:47|:20
- 3 - F 11 OR2 0 2 0 1 |coutf6:64|74390:47|:29
- 1 - F 11 DFFE 0 4 1 2 |coutf6:64|74390:47|2QD (|coutf6:64|74390:47|:31)
- 8 - F 17 DFFE 0 2 1 1 |coutf6:64|74390:47|2QC (|coutf6:64|74390:47|:32)
- 6 - F 11 DFFE 0 2 1 2 |coutf6:64|74390:47|2QB (|coutf6:64|74390:47|:33)
- 4 - C 26 DFFE 0 2 1 3 |coutf6:64|74390:47|2QA (|coutf6:64|74390:47|:34)
- 1 - C 25 OR2 s 0 4 0 1 |MUX4:5|~139~1
- 6 - C 26 OR2 s 0 3 0 1 |MUX4:5|~139~2
- 7 - C 26 OR2 1 3 0 1 |MUX4:5|:139
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\kechengshejitest\cgate.rpt
cgate
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 8/144( 5%) 4/ 72( 5%) 8/ 72( 11%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
D: 7/144( 4%) 5/ 72( 6%) 1/ 72( 1%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 12/144( 8%) 11/ 72( 15%) 3/ 72( 4%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\kechengshejitest\cgate.rpt
cgate
** CLOCK SIGNALS **
Type Fan-out Name
DFF 6 |coutf6:64|74390:45|2QA
DFF 6 |coutf6:64|74390:47|1QA
DFF 6 |coutf6:64|74390:46|2QA
DFF 5 |coutf6:64|74390:45|1QA
LCELL 5 |coutf6:64|over
DFF 5 |coutf6:64|74390:46|1QA
DFF 5 |coutf6:64|74390:47|2QA
DFF 4 |coutf6:64|74390:46|2QB
DFF 4 |coutf6:64|74390:47|1QB
DFF 4 |coutf6:64|74390:47|2QB
DFF 4 |coutf6:64|74390:46|1QB
DFF 4 |coutf6:64|74390:45|2QB
INPUT 4 clk0
DFF 4 |coutf6:64|74390:45|1QB
DFF 4 |cnt10_100:52|74390:14|2QB
DFF 4 |cnt10_100:52|74390:14|2QA
DFF 4 |cnt10_100:52|74390:14|1QB
DFF 4 |cnt10_100:52|74390:14|1QA
LCELL 2 |coutf6:64|:38
LCELL 2 |coutf6:64|:34
LCELL 2 |cnt10_100:52|co10
INPUT 2 test
LCELL 1 |coutf6:64|74390:47|:20
LCELL 1 |coutf6:64|74390:47|:29
LCELL 1 |cnt10_100:52|74390:14|:20
LCELL 1 |cnt10_100:52|74390:14|:29
LCELL 1 |coutf6:64|74390:46|:29
LCELL 1 |coutf6:64|74390:46|:20
LCELL 1 |coutf6:64|:33
LCELL 1 |coutf6:64|:35
LCELL 1 |coutf6:64|74390:45|:29
LCELL 1 |coutf6:64|74390:45|:20
LCELL 1 |coutf6:64|:36
LCELL 1 |coutf6:64|:37
Device-Specific Information: d:\kechengshejitest\cgate.rpt
cgate
** CLEAR SIGNALS **
Type Fan-out Name
DFF 25 |coutf6:64|74194:3|QB
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