📄 cnt10_100.rpt
字号:
- 6 - B 02 AND2 0 3 1 0 :2
- 4 - B 14 OR2 ! 0 4 1 2 :13
- 2 - B 14 DFFE 0 3 0 2 |74390:14|1QD (|74390:14|:3)
- 1 - B 14 DFFE 0 1 0 2 |74390:14|1QC (|74390:14|:5)
- 2 - B 21 DFFE 0 1 0 3 |74390:14|1QB (|74390:14|:6)
- 1 - B 13 DFFE + 0 0 0 3 |74390:14|1QA (|74390:14|:7)
- 5 - B 14 OR2 0 2 0 1 |74390:14|:20
- 1 - B 02 OR2 0 2 0 1 |74390:14|:29
- 2 - B 02 DFFE 0 3 0 2 |74390:14|2QD (|74390:14|:31)
- 3 - B 02 DFFE 0 1 0 2 |74390:14|2QC (|74390:14|:32)
- 2 - B 06 DFFE 0 1 0 3 |74390:14|2QB (|74390:14|:33)
- 2 - B 10 DFFE 0 1 0 3 |74390:14|2QA (|74390:14|:34)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\kechengshejitest\cnt10_100.rpt
cnt10_100
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 7/ 96( 7%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\kechengshejitest\cnt10_100.rpt
cnt10_100
** CLOCK SIGNALS **
Type Fan-out Name
DFF 4 |74390:14|1QB
DFF 4 |74390:14|1QA
DFF 4 |74390:14|2QB
DFF 4 |74390:14|2QA
LCELL 3 :13
INPUT 1 clk
LCELL 1 |74390:14|:20
LCELL 1 |74390:14|:29
Device-Specific Information: d:\kechengshejitest\cnt10_100.rpt
cnt10_100
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 clr
Device-Specific Information: d:\kechengshejitest\cnt10_100.rpt
cnt10_100
** EQUATIONS **
clk : INPUT;
clr : INPUT;
-- Node name is 'co10'
-- Equation name is 'co10', type is output
co10 = _LC4_B14;
-- Node name is 'co100'
-- Equation name is 'co100', type is output
co100 = _LC6_B2;
-- Node name is '|74390:14|:7' = '|74390:14|1QA'
-- Equation name is '_LC1_B13', type is buried
_LC1_B13 = DFFE(!_LC1_B13, GLOBAL(!clk), GLOBAL(!clr), VCC, VCC);
-- Node name is '|74390:14|:6' = '|74390:14|1QB'
-- Equation name is '_LC2_B21', type is buried
_LC2_B21 = DFFE(!_LC2_B21, _LC5_B14, GLOBAL(!clr), VCC, VCC);
-- Node name is '|74390:14|:5' = '|74390:14|1QC'
-- Equation name is '_LC1_B14', type is buried
_LC1_B14 = DFFE(!_LC1_B14, !_LC2_B21, GLOBAL(!clr), VCC, VCC);
-- Node name is '|74390:14|:3' = '|74390:14|1QD'
-- Equation name is '_LC2_B14', type is buried
_LC2_B14 = DFFE( _EQ001, !_LC1_B13, GLOBAL(!clr), VCC, VCC);
_EQ001 = _LC1_B14 & !_LC2_B14 & _LC2_B21;
-- Node name is '|74390:14|:34' = '|74390:14|2QA'
-- Equation name is '_LC2_B10', type is buried
_LC2_B10 = DFFE(!_LC2_B10, !_LC4_B14, GLOBAL(!clr), VCC, VCC);
-- Node name is '|74390:14|:33' = '|74390:14|2QB'
-- Equation name is '_LC2_B6', type is buried
_LC2_B6 = DFFE(!_LC2_B6, _LC1_B2, GLOBAL(!clr), VCC, VCC);
-- Node name is '|74390:14|:32' = '|74390:14|2QC'
-- Equation name is '_LC3_B2', type is buried
_LC3_B2 = DFFE(!_LC3_B2, !_LC2_B6, GLOBAL(!clr), VCC, VCC);
-- Node name is '|74390:14|:31' = '|74390:14|2QD'
-- Equation name is '_LC2_B2', type is buried
_LC2_B2 = DFFE( _EQ002, !_LC2_B10, GLOBAL(!clr), VCC, VCC);
_EQ002 = !_LC2_B2 & _LC2_B6 & _LC3_B2;
-- Node name is '|74390:14|:20'
-- Equation name is '_LC5_B14', type is buried
_LC5_B14 = LCELL( _EQ003);
_EQ003 = _LC2_B14
# !_LC1_B13;
-- Node name is '|74390:14|:29'
-- Equation name is '_LC1_B2', type is buried
_LC1_B2 = LCELL( _EQ004);
_EQ004 = _LC2_B2
# !_LC2_B10;
-- Node name is '~2~1'
-- Equation name is '~2~1', location is LC4_B2, type is buried.
-- synthesized logic cell
_LC4_B2 = LCELL( _EQ005);
_EQ005 = _LC2_B2 & _LC2_B10 & _LC4_B14;
-- Node name is ':2'
-- Equation name is '_LC6_B2', type is buried
_LC6_B2 = LCELL( _EQ006);
_EQ006 = !_LC2_B6 & !_LC3_B2 & _LC4_B2;
-- Node name is ':13'
-- Equation name is '_LC4_B14', type is buried
!_LC4_B14 = _LC4_B14~NOT;
_LC4_B14~NOT = LCELL( _EQ007);
_EQ007 = _LC1_B14
# _LC2_B21
# !_LC2_B14
# !_LC1_B13;
Project Information d:\kechengshejitest\cnt10_100.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 27,670K
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