vgainterface.tan.qmsg

关于VGA显示接口的一些代码可以下载

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clock_25mhz " "Info: Detected ripple clock clock_25mhz as buffer" {  } { { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 67 -1 0 } } { "c:/program files/eda/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/program files/eda/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clock_25mhz" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock0 register address\[0\] memory tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|ram_block1a0~porta_address_reg0 181.42 MHz 5.512 ns Internal " "Info: Clock clock0 has Internal fmax of 181.42 MHz between source register address\[0\] and destination memory tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|ram_block1a0~porta_address_reg0 (period= 5.512 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.754 ns + Longest register memory " "Info: + Longest register to memory delay is 1.754 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns address\[0\] 1 REG LC_X15_Y7_N6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y7_N6; Fanout = 4; REG Node = 'address\[0\]'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { address[0] } "NODE_NAME" } } } { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 215 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.459 ns) + CELL(0.295 ns) 1.754 ns tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|ram_block1a0~porta_address_reg0 2 MEM M4K_X13_Y8 1 " "Info: 2: + IC(1.459 ns) + CELL(0.295 ns) = 1.754 ns; Loc. = M4K_X13_Y8; Fanout = 1; MEM Node = 'tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "1.754 ns" { address[0] tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } } { "F:/program_test/vgainterface/db/altsyncram_qcr.tdf" "" "" { Text "F:/program_test/vgainterface/db/altsyncram_qcr.tdf" 42 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.295 ns 16.82 % " "Info: Total cell delay = 0.295 ns ( 16.82 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.459 ns 83.18 % " "Info: Total interconnect delay = 1.459 ns ( 83.18 % )" {  } {  } 0}  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "1.754 ns" { address[0] tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.513 ns - Smallest " "Info: - Smallest clock skew is -3.513 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock0 destination 8.645 ns + Shortest memory " "Info: + Shortest clock path from clock clock0 to destination memory is 8.645 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns clock0 1 CLK PIN_123 51 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_123; Fanout = 51; CLK Node = 'clock0'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { clock0 } "NODE_NAME" } } } { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.954 ns) + CELL(0.556 ns) 8.645 ns tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|ram_block1a0~porta_address_reg0 2 MEM M4K_X13_Y8 1 " "Info: 2: + IC(6.954 ns) + CELL(0.556 ns) = 8.645 ns; Loc. = M4K_X13_Y8; Fanout = 1; MEM Node = 'tsinghua:u1\|altsyncram:altsyncram_component\|altsyncram_qcr:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "7.510 ns" { clock0 tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } } { "F:/program_test/vgainterface/db/altsyncram_qcr.tdf" "" "" { Text "F:/program_test/vgainterface/db/altsyncram_qcr.tdf" 42 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.691 ns 19.56 % " "Info: Total cell delay = 1.691 ns ( 19.56 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.954 ns 80.44 % " "Info: Total interconnect delay = 6.954 ns ( 80.44 % )" {  } {  } 0}  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "8.645 ns" { clock0 tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock0 source 12.158 ns - Longest register " "Info: - Longest clock path from clock clock0 to source register is 12.158 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns clock0 1 CLK PIN_123 51 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_123; Fanout = 51; CLK Node = 'clock0'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { clock0 } "NODE_NAME" } } } { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.942 ns) + CELL(0.720 ns) 8.797 ns clock_25mhz 2 REG LC_X8_Y10_N2 44 " "Info: 2: + IC(6.942 ns) + CELL(0.720 ns) = 8.797 ns; Loc. = LC_X8_Y10_N2; Fanout = 44; REG Node = 'clock_25mhz'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "7.662 ns" { clock0 clock_25mhz } "NODE_NAME" } } } { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 67 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.814 ns) + CELL(0.547 ns) 12.158 ns address\[0\] 3 REG LC_X15_Y7_N6 4 " "Info: 3: + IC(2.814 ns) + CELL(0.547 ns) = 12.158 ns; Loc. = LC_X15_Y7_N6; Fanout = 4; REG Node = 'address\[0\]'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "3.361 ns" { clock_25mhz address[0] } "NODE_NAME" } } } { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 215 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.402 ns 19.76 % " "Info: Total cell delay = 2.402 ns ( 19.76 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.756 ns 80.24 % " "Info: Total interconnect delay = 9.756 ns ( 80.24 % )" {  } {  } 0}  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "12.158 ns" { clock0 clock_25mhz address[0] } "NODE_NAME" } } }  } 0}  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "8.645 ns" { clock0 tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } } { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "12.158 ns" { clock0 clock_25mhz address[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 215 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.072 ns + " "Info: + Micro setup delay of destination is 0.072 ns" {  } { { "F:/program_test/vgainterface/db/altsyncram_qcr.tdf" "" "" { Text "F:/program_test/vgainterface/db/altsyncram_qcr.tdf" 42 2 0 } }  } 0}  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "1.754 ns" { address[0] tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } } { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "8.645 ns" { clock0 tsinghua:u1|altsyncram:altsyncram_component|altsyncram_qcr:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } } { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "12.158 ns" { clock0 clock_25mhz address[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock2 register count_z\[0\] register count_z\[4\] 311.43 MHz 3.211 ns Internal " "Info: Clock clock2 has Internal fmax of 311.43 MHz between source register count_z\[0\] and destination register count_z\[4\] (period= 3.211 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.009 ns + Longest register register " "Info: + Longest register to register delay is 3.009 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count_z\[0\] 1 REG LC_X12_Y10_N4 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y10_N4; Fanout = 9; REG Node = 'count_z\[0\]'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { count_z[0] } "NODE_NAME" } } } { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 54 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.005 ns) + CELL(0.443 ns) 1.448 ns add~22COUT1 2 COMB LC_X12_Y10_N5 2 " "Info: 2: + IC(1.005 ns) + CELL(0.443 ns) = 1.448 ns; Loc. = LC_X12_Y10_N5; Fanout = 2; COMB Node = 'add~22COUT1'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "1.448 ns" { count_z[0] add~22COUT1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 1.510 ns add~23COUT1 3 COMB LC_X12_Y10_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.062 ns) = 1.510 ns; Loc. = LC_X12_Y10_N6; Fanout = 2; COMB Node = 'add~23COUT1'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "0.062 ns" { add~22COUT1 add~23COUT1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 1.572 ns add~24COUT1 4 COMB LC_X12_Y10_N7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.062 ns) = 1.572 ns; Loc. = LC_X12_Y10_N7; Fanout = 2; COMB Node = 'add~24COUT1'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "0.062 ns" { add~23COUT1 add~24COUT1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 1.634 ns add~25COUT1 5 COMB LC_X12_Y10_N8 1 " "Info: 5: + IC(0.000 ns) + CELL(0.062 ns) = 1.634 ns; Loc. = LC_X12_Y10_N8; Fanout = 1; COMB Node = 'add~25COUT1'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "0.062 ns" { add~24COUT1 add~25COUT1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.468 ns) 2.102 ns add~26 6 COMB LC_X12_Y10_N9 1 " "Info: 6: + IC(0.000 ns) + CELL(0.468 ns) = 2.102 ns; Loc. = LC_X12_Y10_N9; Fanout = 1; COMB Node = 'add~26'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "0.468 ns" { add~25COUT1 add~26 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.339 ns) + CELL(0.568 ns) 3.009 ns count_z\[4\] 7 REG LC_X12_Y10_N3 10 " "Info: 7: + IC(0.339 ns) + CELL(0.568 ns) = 3.009 ns; Loc. = LC_X12_Y10_N3; Fanout = 10; REG Node = 'count_z\[4\]'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "0.907 ns" { add~26 count_z[4] } "NODE_NAME" } } } { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 54 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.665 ns 55.33 % " "Info: Total cell delay = 1.665 ns ( 55.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.344 ns 44.67 % " "Info: Total interconnect delay = 1.344 ns ( 44.67 % )" {  } {  } 0}  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "3.009 ns" { count_z[0] add~22COUT1 add~23COUT1 add~24COUT1 add~25COUT1 add~26 count_z[4] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock2 destination 8.353 ns + Shortest register " "Info: + Shortest clock path from clock clock2 to destination register is 8.353 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns clock2 1 CLK PIN_124 5 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_124; Fanout = 5; CLK Node = 'clock2'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { clock2 } "NODE_NAME" } } } { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.671 ns) + CELL(0.547 ns) 8.353 ns count_z\[4\] 2 REG LC_X12_Y10_N3 10 " "Info: 2: + IC(6.671 ns) + CELL(0.547 ns) = 8.353 ns; Loc. = LC_X12_Y10_N3; Fanout = 10; REG Node = 'count_z\[4\]'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "7.218 ns" { clock2 count_z[4] } "NODE_NAME" } } } { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 54 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.682 ns 20.14 % " "Info: Total cell delay = 1.682 ns ( 20.14 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.671 ns 79.86 % " "Info: Total interconnect delay = 6.671 ns ( 79.86 % )" {  } {  } 0}  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "8.353 ns" { clock2 count_z[4] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock2 source 8.353 ns - Longest register " "Info: - Longest clock path from clock clock2 to source register is 8.353 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns clock2 1 CLK PIN_124 5 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_124; Fanout = 5; CLK Node = 'clock2'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "" { clock2 } "NODE_NAME" } } } { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.671 ns) + CELL(0.547 ns) 8.353 ns count_z\[0\] 2 REG LC_X12_Y10_N4 9 " "Info: 2: + IC(6.671 ns) + CELL(0.547 ns) = 8.353 ns; Loc. = LC_X12_Y10_N4; Fanout = 9; REG Node = 'count_z\[0\]'" {  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "7.218 ns" { clock2 count_z[0] } "NODE_NAME" } } } { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 54 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.682 ns 20.14 % " "Info: Total cell delay = 1.682 ns ( 20.14 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.671 ns 79.86 % " "Info: Total interconnect delay = 6.671 ns ( 79.86 % )" {  } {  } 0}  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "8.353 ns" { clock2 count_z[0] } "NODE_NAME" } } }  } 0}  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "8.353 ns" { clock2 count_z[4] } "NODE_NAME" } } } { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "8.353 ns" { clock2 count_z[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 54 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "F:/program_test/vgainterface/vgainterface.vhd" "" "" { Text "F:/program_test/vgainterface/vgainterface.vhd" 54 -1 0 } }  } 0}  } { { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "3.009 ns" { count_z[0] add~22COUT1 add~23COUT1 add~24COUT1 add~25COUT1 add~26 count_z[4] } "NODE_NAME" } } } { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "8.353 ns" { clock2 count_z[4] } "NODE_NAME" } } } { "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" "" "" { Report "F:/program_test/vgainterface/db/vgainterface_cmp.qrpt" Compiler "vgainterface" "UNKNOWN" "V1" "F:/program_test/vgainterface/db/vgainterface.quartus_db" { Floorplan "" "" "8.353 ns" { clock2 count_z[0] } "NODE_NAME" } } }  } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clock0 6 " "Warning: Circuit may not operate. Detected 6 non-operational path(s) clocked by clock clock0 with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}