vgal.tan.rpt

实现模拟阴极射线管的彩色显示的行扫描和场扫描

; N/A   ; None         ; 13.969 ns  ; CC[2]  ; B  ; CLK        ;
; N/A   ; None         ; 13.258 ns  ; CC[2]  ; G  ; CLK        ;
; N/A   ; None         ; 12.801 ns  ; CC[4]  ; HS ; CLK        ;
; N/A   ; None         ; 12.677 ns  ; MMD[1] ; R  ; MD         ;
; N/A   ; None         ; 12.605 ns  ; CC[3]  ; HS ; CLK        ;
; N/A   ; None         ; 12.512 ns  ; MMD[0] ; R  ; MD         ;
; N/A   ; None         ; 12.093 ns  ; MMD[1] ; G  ; MD         ;
; N/A   ; None         ; 11.928 ns  ; MMD[0] ; G  ; MD         ;
; N/A   ; None         ; 11.742 ns  ; MMD[0] ; B  ; MD         ;
; N/A   ; None         ; 11.654 ns  ; MMD[1] ; B  ; MD         ;
+-------+--------------+------------+--------+----+------------+


+---------------------------------------------------------+
; tpd                                                     ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A   ; None              ; 8.113 ns        ; MD   ; R  ;
; N/A   ; None              ; 7.570 ns        ; MD   ; B  ;
; N/A   ; None              ; 6.857 ns        ; MD   ; G  ;
+-------+-------------------+-----------------+------+----+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Sun Apr 06 15:17:55 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off VGAL -c VGAL --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
    Info: Assuming node "MD" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "FS[3]" as buffer
    Info: Detected ripple clock "CC[4]" as buffer
Info: Clock "CLK" has Internal fmax of 227.12 MHz between source register "LL[0]" and destination register "LL[5]" (period= 4.403 ns)
    Info: + Longest register to register delay is 4.142 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y12_N2; Fanout = 8; REG Node = 'LL[0]'
        Info: 2: + IC(1.292 ns) + CELL(0.564 ns) = 1.856 ns; Loc. = LC_X16_Y11_N0; Fanout = 2; COMB Node = 'Add3~147'
        Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.934 ns; Loc. = LC_X16_Y11_N1; Fanout = 2; COMB Node = 'Add3~149'
        Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 2.012 ns; Loc. = LC_X16_Y11_N2; Fanout = 2; COMB Node = 'Add3~145'
        Info: 5: + IC(0.000 ns) + CELL(0.078 ns) = 2.090 ns; Loc. = LC_X16_Y11_N3; Fanout = 2; COMB Node = 'Add3~143'
        Info: 6: + IC(0.000 ns) + CELL(0.178 ns) = 2.268 ns; Loc. = LC_X16_Y11_N4; Fanout = 4; COMB Node = 'Add3~141'
        Info: 7: + IC(0.000 ns) + CELL(0.621 ns) = 2.889 ns; Loc. = LC_X16_Y11_N5; Fanout = 1; COMB Node = 'Add3~138'
        Info: 8: + IC(0.775 ns) + CELL(0.478 ns) = 4.142 ns; Loc. = LC_X17_Y11_N8; Fanout = 9; REG Node = 'LL[5]'
        Info: Total cell delay = 2.075 ns ( 50.10 % )
        Info: Total interconnect delay = 2.067 ns ( 49.90 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 11.973 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 4; CLK Node = 'CLK'
            Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y6_N2; Fanout = 8; REG Node = 'FS[3]'
            Info: 3: + IC(3.456 ns) + CELL(0.935 ns) = 7.355 ns; Loc. = LC_X11_Y6_N9; Fanout = 15; REG Node = 'CC[4]'
            Info: 4: + IC(3.907 ns) + CELL(0.711 ns) = 11.973 ns; Loc. = LC_X17_Y11_N8; Fanout = 9; REG Node = 'LL[5]'
            Info: Total cell delay = 4.050 ns ( 33.83 % )
            Info: Total interconnect delay = 7.923 ns ( 66.17 % )
        Info: - Longest clock path from clock "CLK" to source register is 11.973 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 4; CLK Node = 'CLK'
            Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y6_N2; Fanout = 8; REG Node = 'FS[3]'
            Info: 3: + IC(3.456 ns) + CELL(0.935 ns) = 7.355 ns; Loc. = LC_X11_Y6_N9; Fanout = 15; REG Node = 'CC[4]'
            Info: 4: + IC(3.907 ns) + CELL(0.711 ns) = 11.973 ns; Loc. = LC_X16_Y12_N2; Fanout = 8; REG Node = 'LL[0]'
            Info: Total cell delay = 4.050 ns ( 33.83 % )
            Info: Total interconnect delay = 7.923 ns ( 66.17 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: Clock "MD" Internal fmax is restricted to 275.03 MHz between source register "MMD[1]" and destination register "MMD[0]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.064 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y11_N9; Fanout = 4; REG Node = 'MMD[1]'
            Info: 2: + IC(0.586 ns) + CELL(0.478 ns) = 1.064 ns; Loc. = LC_X15_Y11_N5; Fanout = 8; REG Node = 'MMD[0]'
            Info: Total cell delay = 0.478 ns ( 44.92 % )
            Info: Total interconnect delay = 0.586 ns ( 55.08 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "MD" to destination register is 2.782 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 5; CLK Node = 'MD'
                Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X15_Y11_N5; Fanout = 8; REG Node = 'MMD[0]'
                Info: Total cell delay = 2.180 ns ( 78.36 % )
                Info: Total interconnect delay = 0.602 ns ( 21.64 % )
            Info: - Longest clock path from clock "MD" to source register is 2.782 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 5; CLK Node = 'MD'
                Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X15_Y11_N9; Fanout = 4; REG Node = 'MMD[1]'
                Info: Total cell delay = 2.180 ns ( 78.36 % )
                Info: Total interconnect delay = 0.602 ns ( 21.64 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "CLK" to destination pin "B" through register "LL[2]" is 23.851 ns
    Info: + Longest clock path from clock "CLK" to source register is 11.973 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 4; CLK Node = 'CLK'
        Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y6_N2; Fanout = 8; REG Node = 'FS[3]'
        Info: 3: + IC(3.456 ns) + CELL(0.935 ns) = 7.355 ns; Loc. = LC_X11_Y6_N9; Fanout = 15; REG Node = 'CC[4]'
        Info: 4: + IC(3.907 ns) + CELL(0.711 ns) = 11.973 ns; Loc. = LC_X17_Y11_N1; Fanout = 6; REG Node = 'LL[2]'
        Info: Total cell delay = 4.050 ns ( 33.83 % )
        Info: Total interconnect delay = 7.923 ns ( 66.17 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 11.654 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y11_N1; Fanout = 6; REG Node = 'LL[2]'
        Info: 2: + IC(1.240 ns) + CELL(0.590 ns) = 1.830 ns; Loc. = LC_X15_Y11_N6; Fanout = 1; COMB Node = 'GRB~2104'
        Info: 3: + IC(0.423 ns) + CELL(0.114 ns) = 2.367 ns; Loc. = LC_X15_Y11_N8; Fanout = 1; COMB Node = 'GRB~2105'
        Info: 4: + IC(2.059 ns) + CELL(0.292 ns) = 4.718 ns; Loc. = LC_X15_Y11_N2; Fanout = 1; COMB Node = 'GRB~2099'
        Info: 5: + IC(1.719 ns) + CELL(0.590 ns) = 7.027 ns; Loc. = LC_X12_Y7_N5; Fanout = 1; COMB Node = 'GRB~2103'
        Info: 6: + IC(2.503 ns) + CELL(2.124 ns) = 11.654 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'B'
        Info: Total cell delay = 3.710 ns ( 31.83 % )
        Info: Total interconnect delay = 7.944 ns ( 68.17 % )
Info: Longest tpd from source pin "MD" to destination pin "R" is 8.113 ns
    Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 5; CLK Node = 'MD'
    Info: 2: + IC(1.184 ns) + CELL(0.292 ns) = 2.945 ns; Loc. = LC_X12_Y7_N0; Fanout = 1; COMB Node = 'GRB~2091'
    Info: 3: + IC(0.426 ns) + CELL(0.114 ns) = 3.485 ns; Loc. = LC_X12_Y7_N7; Fanout = 1; COMB Node = 'GRB~2092'
    Info: 4: + IC(2.504 ns) + CELL(2.124 ns) = 8.113 ns; Loc. = PIN_85; Fanout = 0; PIN Node = 'R'
    Info: Total cell delay = 3.999 ns ( 49.29 % )
    Info: Total interconnect delay = 4.114 ns ( 50.71 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 110 megabytes of memory during processing
    Info: Processing ended: Sun Apr 06 15:17:56 2008
    Info: Elapsed time: 00:00:01