📄 vgal.tan.qmsg
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{ "Info" "ITDB_FULL_TPD_RESULT" "MD R 8.113 ns Longest " "Info: Longest tpd from source pin \"MD\" to destination pin \"R\" is 8.113 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns MD 1 CLK PIN_16 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 5; CLK Node = 'MD'" { } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { MD } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.184 ns) + CELL(0.292 ns) 2.945 ns GRB~2091 2 COMB LC_X12_Y7_N0 1 " "Info: 2: + IC(1.184 ns) + CELL(0.292 ns) = 2.945 ns; Loc. = LC_X12_Y7_N0; Fanout = 1; COMB Node = 'GRB~2091'" { } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.476 ns" { MD GRB~2091 } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.426 ns) + CELL(0.114 ns) 3.485 ns GRB~2092 3 COMB LC_X12_Y7_N7 1 " "Info: 3: + IC(0.426 ns) + CELL(0.114 ns) = 3.485 ns; Loc. = LC_X12_Y7_N7; Fanout = 1; COMB Node = 'GRB~2092'" { } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.540 ns" { GRB~2091 GRB~2092 } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.504 ns) + CELL(2.124 ns) 8.113 ns R 4 PIN PIN_85 0 " "Info: 4: + IC(2.504 ns) + CELL(2.124 ns) = 8.113 ns; Loc. = PIN_85; Fanout = 0; PIN Node = 'R'" { } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.628 ns" { GRB~2092 R } "NODE_NAME" } } { "VGAL.vhd" "" { Text "D:/TEST/VGAL.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.999 ns ( 49.29 % ) " "Info: Total cell delay = 3.999 ns ( 49.29 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.114 ns ( 50.71 % ) " "Info: Total interconnect delay = 4.114 ns ( 50.71 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.113 ns" { MD GRB~2091 GRB~2092 R } "NODE_NAME" } } { "d:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/quartus/bin/Technology_Viewer.qrui" "8.113 ns" { MD {} MD~out0 {} GRB~2091 {} GRB~2092 {} R {} } { 0.000ns 0.000ns 1.184ns 0.426ns 2.504ns } { 0.000ns 1.469ns 0.292ns 0.114ns 2.124ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "110 " "Info: Allocated 110 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 06 15:17:56 2008 " "Info: Processing ended: Sun Apr 06 15:17:56 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
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